Skip site navigation (1)Skip section navigation (2)
Date:      Wed, 22 May 1996 23:26:51 +0900 (JST)
From:      Michael Hancock <michaelh@cet.co.jp>
To:        Terry Lambert <terry@lambert.org>
Cc:        bsdi-users@bsdi.com, freebsd-hackers@freebsd.com
Subject:   Re: ISDN Compression Load on CPU
Message-ID:  <Pine.SV4.3.93.960522231651.21225A-100000@parkplace.cet.co.jp>
In-Reply-To: <199605202119.OAA28500@phaeton.artisoft.com>

next in thread | previous in thread | raw e-mail | index | archive | help
On Mon, 20 May 1996, Terry Lambert wrote:

> > SDLComm has a new PCI card called the RISCom/Pri.  Primary rate has 23
> > 64Kbps B-Channels.  I wonder how many cards can be put into a P90 box
> > running BSD Unix before the compression overloads the CPU? 
> 
> The RISC CPU you mean.. dunno.

I still don't know if the card handle compression or not.  I'm waiting for
an answer. 

It will manage separate buffers in host RAM for each channel.  It also
uses a host buffer for control.  If it doesn't do compression and the host
has to do it, I wonder what the limits are when 23 64Kbps streams of
compressed data are coming in?

It would be cool to be able to put 2 of these cards into a PC and handle
46 incoming ISDN connections. 

The following is from http://www.sdlcomm.com/pri.htm...

----------------
       LOW COST ISDN PRI ADAPTER FOR THE PCI BUS

The RISCom/Pri is a low cost ISDN and Channelized T1/E1 Adapter for the
PCI Bus featuring a modular full function T1 or E1 Interface. The
RISCom/Pri is ideal for applications such as PC Based Multi-protocol
Routers running such protocols as Primary Rate ISDN , Frame Relay, X.25
and PPP.

32-Bit PCI Bus Master

The RISCom/Pri operates as a 32-bit direct PCI Bus Master managing a
separate buffer for each HDLC stream directly in PC Host RAM. The PC Host
configures and manages the PRI controller via a command buffer in PC Host
RAM. 

Intelligent PRI Controller

The key component on the RISCom/Pri card is the Multi-Channel HDLC (PRI) 
Controller which manages 24 or 32 separate HDLC streams of data which are
presented by the T1 or E1 interface as (DS0s) time slots. For Primary Rate
applications, the DS0s are organized as a single D channel plus 23B
channels for T1 or 30B channels for E1. The PRI controller is configurable
for managing groups of multiple DS0s (nx64Kbps) hence supporting
bandwidths of nx64Kbps.

----------------------
 
> > How heavy is the computational load of something like STAC compression?
> 
> As a percentage of CPU: depends on your CPU.
> 
> As a percentage of file I/O overhead: ~17%, assuming average cache
> locality, degrading to ~36% for cache-busting (like IOZone).  This
> was on a 486 DX/2-66, so your mileage may vary.
> 

-mike hancock





Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?Pine.SV4.3.93.960522231651.21225A-100000>