Date: Sat, 2 Aug 1997 00:27:48 +0200 From: Stefan Esser <se@FreeBSD.ORG> To: Andrew Gallatin <gallatin@cs.duke.edu> Cc: freebsd-current@FreeBSD.ORG, Stefan Esser <se@FreeBSD.ORG> Subject: Re: code talks: announcing EIDE bus master patches Message-ID: <19970802002748.50831@mi.uni-koeln.de> In-Reply-To: <199707302036.QAA23330@hurricane.cs.duke.edu>; from Andrew Gallatin on Wed, Jul 30, 1997 at 04:36:30PM -0400 References: <19970729210723.18104@mi.uni-koeln.de> <199707291949.VAA00271@sos.freebsd.dk> <19970729221036.52544@mi.uni-koeln.de> <199707301924.PAA08936@hurricane.cs.duke.edu> <19970730220038.02422@mi.uni-koeln.de> <199707302036.QAA23330@hurricane.cs.duke.edu>
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On Jul 30, Andrew Gallatin <gallatin@CS.Duke.EDU> wrote:
> > But in any case: In order to use PCI burst transfers, you
> > have to write to sequential memory addresses, e.g. to some
> > double-mapped SRAM buffer.
>
> Double-mapped? What does that mean?
Sorry, it was too late in then night, and I just
could not find the correct word. What I meant was
"dual-ported", but I think you already guessed
that ...
> > That's *very* different from an I/O port, and you should be able
> > to copy data to that SRAM at a much higher rate than 8 or 13MB/s!
>
> Right. The Natoma is using burst transfers for PIO writes and getting
> nearly 30MB/sec. Its apparently not bursting the reads, and is
> getting only 8MB/sec. How do you get an Intel to burst reads? I
> didn't think they could support multiple outstanding reads. I know
> that alphas do, and there are apparently tricks you can use to make an
> alpha burst reads & get 50MB/sec bandwidth, but I wasn't aware of
> Intels that could get better than 15MB/sec for PIO reads.
Yes, AFAIK there is no Intel (or other P5 or PPro
compatible) chip set, that supports burst reads.
Burst writes are easy (the FIFO in the host to PCI
bridge checks that sequential addresses are written
to, and can use the byte enables if not thea full
DWORD is to be stored), but the host to PCI bridge
had to perform a read-ahead for read bursts ...
Most PCI bus-master controllers do not only know
how to initiate burst transfers in either direction,
they will also use read-line and read-multiple (and
write-and-invalidate) where appropriate to reduce
latencies (when crossing PCI bridges) and impact on
the CPU.
> I'm getting most of my information from emperical results obtained
> with our P6's and Alphas using Myrinet cards, plus the DEC PCI Pamette
> paper ("Systems Performance Measurement on PCI Pamette", Laurent Moll,
> Mark Shand, Fccm97, ftp://pam.devinci.fr/pub/pamette/fccm97.ps.gz).
Regards, STefan
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