Date: Mon, 19 Feb 2018 22:19:45 +0000 (UTC) From: Jeff Roberson <jeff@FreeBSD.org> To: src-committers@freebsd.org, svn-src-user@freebsd.org Subject: svn commit: r329607 - in user/jeff/numa/sys: amd64/amd64 amd64/conf amd64/include amd64/linux32 amd64/vmm/amd amd64/vmm/intel arm/allwinner arm/arm arm/conf arm/freescale/imx arm/include arm64/arm6... Message-ID: <201802192219.w1JMJjJ0077689@repo.freebsd.org>
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Author: jeff Date: Mon Feb 19 22:19:44 2018 New Revision: 329607 URL: https://svnweb.freebsd.org/changeset/base/329607 Log: Merge from head Added: user/jeff/numa/sys/compat/linuxkpi/common/include/linux/dcache.h - copied unchanged from r329605, head/sys/compat/linuxkpi/common/include/linux/dcache.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/irqreturn.h - copied unchanged from r329605, head/sys/compat/linuxkpi/common/include/linux/irqreturn.h user/jeff/numa/sys/dev/bhnd/siba/siba_eromvar.h - copied unchanged from r329605, head/sys/dev/bhnd/siba/siba_eromvar.h user/jeff/numa/sys/dev/mthca/ - copied from r329605, head/sys/dev/mthca/ user/jeff/numa/sys/modules/i2c/ofw_iicbus/ - copied from r329605, head/sys/modules/i2c/ofw_iicbus/ user/jeff/numa/sys/modules/imx/ - copied from r329605, head/sys/modules/imx/ user/jeff/numa/sys/modules/mthca/ - copied from r329605, head/sys/modules/mthca/ user/jeff/numa/sys/modules/spi/ - copied from r329605, head/sys/modules/spi/ user/jeff/numa/sys/ofed/include/uapi/rdma/mthca-abi.h - copied unchanged from r329605, head/sys/ofed/include/uapi/rdma/mthca-abi.h Deleted: user/jeff/numa/sys/amd64/include/varargs.h user/jeff/numa/sys/i386/include/varargs.h user/jeff/numa/sys/mips/include/varargs.h user/jeff/numa/sys/powerpc/include/varargs.h user/jeff/numa/sys/sparc64/include/varargs.h Modified: user/jeff/numa/sys/amd64/amd64/efirt_machdep.c (contents, props changed) user/jeff/numa/sys/amd64/amd64/pmap.c user/jeff/numa/sys/amd64/conf/NOTES user/jeff/numa/sys/amd64/include/asmacros.h user/jeff/numa/sys/amd64/include/pcpu.h user/jeff/numa/sys/amd64/linux32/linux32_dummy.c user/jeff/numa/sys/amd64/vmm/amd/amdvi_hw.c user/jeff/numa/sys/amd64/vmm/amd/amdvi_priv.h user/jeff/numa/sys/amd64/vmm/amd/ivrs_drv.c user/jeff/numa/sys/amd64/vmm/amd/svm.c user/jeff/numa/sys/amd64/vmm/amd/svm_support.S user/jeff/numa/sys/amd64/vmm/intel/vmcs.c user/jeff/numa/sys/amd64/vmm/intel/vmx.h user/jeff/numa/sys/amd64/vmm/intel/vmx_support.S user/jeff/numa/sys/arm/allwinner/aw_mmc.c user/jeff/numa/sys/arm/arm/gic_acpi.c user/jeff/numa/sys/arm/arm/pmap-v6.c user/jeff/numa/sys/arm/conf/IMX53 user/jeff/numa/sys/arm/conf/IMX6 user/jeff/numa/sys/arm/freescale/imx/imx6_machdep.c user/jeff/numa/sys/arm/freescale/imx/imx_i2c.c user/jeff/numa/sys/arm/include/_types.h user/jeff/numa/sys/arm64/arm64/efirt_machdep.c user/jeff/numa/sys/arm64/arm64/pmap.c user/jeff/numa/sys/arm64/include/_types.h user/jeff/numa/sys/cam/cam_periph.c user/jeff/numa/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu.c user/jeff/numa/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/dmu.h user/jeff/numa/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zio.h user/jeff/numa/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_geom.c user/jeff/numa/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ctldir.c user/jeff/numa/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c user/jeff/numa/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zio.c user/jeff/numa/sys/compat/freebsd32/freebsd32_misc.c user/jeff/numa/sys/compat/freebsd32/freebsd32_proto.h user/jeff/numa/sys/compat/freebsd32/freebsd32_syscall.h user/jeff/numa/sys/compat/freebsd32/freebsd32_syscalls.c user/jeff/numa/sys/compat/freebsd32/freebsd32_sysent.c user/jeff/numa/sys/compat/freebsd32/freebsd32_systrace_args.c user/jeff/numa/sys/compat/freebsd32/syscalls.master user/jeff/numa/sys/compat/linux/linux_file.c user/jeff/numa/sys/compat/linux/linux_ioctl.c user/jeff/numa/sys/compat/linux/linux_ipc.c user/jeff/numa/sys/compat/linux/linux_mib.c user/jeff/numa/sys/compat/linux/linux_signal.c user/jeff/numa/sys/compat/linux/linux_socket.c user/jeff/numa/sys/compat/linux/linux_stats.c user/jeff/numa/sys/compat/linux/linux_sysctl.c user/jeff/numa/sys/compat/linuxkpi/common/include/asm/atomic.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/compiler.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/device.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/fs.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/gfp.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/interrupt.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/kernel.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/kref.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/ktime.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/list.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/lockdep.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/mm.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/mm_types.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/mutex.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/pid.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/printk.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/radix-tree.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/rcupdate.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/slab.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/spinlock.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/string.h user/jeff/numa/sys/compat/linuxkpi/common/include/linux/uaccess.h user/jeff/numa/sys/compat/linuxkpi/common/src/linux_compat.c user/jeff/numa/sys/compat/linuxkpi/common/src/linux_hrtimer.c user/jeff/numa/sys/compat/linuxkpi/common/src/linux_radix.c user/jeff/numa/sys/compat/linuxkpi/common/src/linux_tasklet.c user/jeff/numa/sys/conf/NOTES user/jeff/numa/sys/conf/files user/jeff/numa/sys/conf/kern.post.mk user/jeff/numa/sys/conf/kmod.mk user/jeff/numa/sys/conf/options user/jeff/numa/sys/contrib/ck/include/ck_md.h user/jeff/numa/sys/contrib/dev/acpica/include/actbl2.h user/jeff/numa/sys/contrib/zstd/lib/freebsd/stdlib.h user/jeff/numa/sys/contrib/zstd/lib/freebsd/zstd_kfreebsd.h user/jeff/numa/sys/dev/bhnd/siba/siba.c user/jeff/numa/sys/dev/bhnd/siba/siba_erom.c user/jeff/numa/sys/dev/bhnd/siba/siba_subr.c user/jeff/numa/sys/dev/bhnd/siba/sibavar.h user/jeff/numa/sys/dev/bwn/if_bwn.c user/jeff/numa/sys/dev/bwn/if_bwn_debug.h user/jeff/numa/sys/dev/bwn/if_bwn_phy_g.c user/jeff/numa/sys/dev/gpio/gpiobusvar.h user/jeff/numa/sys/dev/gpio/ofw_gpiobus.c user/jeff/numa/sys/dev/iicbus/iicbus.h user/jeff/numa/sys/dev/iicbus/ofw_iicbus.c user/jeff/numa/sys/dev/mpr/mpr.c user/jeff/numa/sys/dev/mpr/mpr_sas.c user/jeff/numa/sys/dev/mpr/mprvar.h user/jeff/numa/sys/dev/mps/mps.c user/jeff/numa/sys/dev/mps/mps_sas.c user/jeff/numa/sys/dev/mps/mpsvar.h user/jeff/numa/sys/dev/mxge/if_mxge.c user/jeff/numa/sys/dev/ofw/ofw_standard.c user/jeff/numa/sys/dev/pci/hostb_pci.c user/jeff/numa/sys/dev/pci/pci.c user/jeff/numa/sys/dev/pci/pci_if.m user/jeff/numa/sys/dev/pci/pci_private.h user/jeff/numa/sys/dev/pci/pcivar.h user/jeff/numa/sys/dev/pci/vga_pci.c user/jeff/numa/sys/dev/sdhci/fsl_sdhci.c user/jeff/numa/sys/dev/spibus/ofw_spibus.c user/jeff/numa/sys/dev/spibus/spibusvar.h user/jeff/numa/sys/dev/usb/controller/ehci_imx.c user/jeff/numa/sys/dev/usb/quirk/usb_quirk.c user/jeff/numa/sys/dev/usb/usb_lookup.c user/jeff/numa/sys/dev/usb/usbdevs user/jeff/numa/sys/dev/usb/usbdi.h user/jeff/numa/sys/dev/virtio/virtio.c user/jeff/numa/sys/dev/virtio/virtio.h user/jeff/numa/sys/dev/virtio/virtio_bus_if.m user/jeff/numa/sys/dev/virtio/virtqueue.c user/jeff/numa/sys/dev/virtio/virtqueue.h user/jeff/numa/sys/geom/eli/g_eli.c user/jeff/numa/sys/geom/geom_io.c user/jeff/numa/sys/geom/journal/g_journal_ufs.c user/jeff/numa/sys/geom/label/g_label_ufs.c user/jeff/numa/sys/geom/part/g_part.c user/jeff/numa/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.c user/jeff/numa/sys/i386/conf/NOTES user/jeff/numa/sys/i386/i386/pmap.c user/jeff/numa/sys/i386/linux/imgact_linux.c user/jeff/numa/sys/i386/linux/linux_dummy.c user/jeff/numa/sys/i386/linux/linux_machdep.c user/jeff/numa/sys/i386/linux/linux_ptrace.c user/jeff/numa/sys/i386/linux/linux_sysvec.c user/jeff/numa/sys/kern/kern_exit.c user/jeff/numa/sys/kern/kern_fork.c user/jeff/numa/sys/kern/kern_mutex.c user/jeff/numa/sys/kern/kern_rwlock.c user/jeff/numa/sys/kern/kern_shutdown.c user/jeff/numa/sys/kern/kern_sig.c user/jeff/numa/sys/kern/kern_sx.c user/jeff/numa/sys/kern/kern_time.c user/jeff/numa/sys/kern/subr_clock.c user/jeff/numa/sys/kern/subr_compressor.c user/jeff/numa/sys/kern/subr_rtc.c user/jeff/numa/sys/kern/sys_capability.c user/jeff/numa/sys/kern/sysv_msg.c user/jeff/numa/sys/kern/sysv_sem.c user/jeff/numa/sys/kern/sysv_shm.c user/jeff/numa/sys/kern/vfs_acl.c user/jeff/numa/sys/kern/vfs_bio.c user/jeff/numa/sys/kgssapi/gss_impl.c user/jeff/numa/sys/libkern/strcmp.c user/jeff/numa/sys/libkern/strncat.c user/jeff/numa/sys/libkern/strncpy.c user/jeff/numa/sys/libkern/strsep.c user/jeff/numa/sys/libkern/strstr.c user/jeff/numa/sys/mips/include/_types.h user/jeff/numa/sys/mips/include/stdarg.h user/jeff/numa/sys/mips/mips/pmap.c user/jeff/numa/sys/modules/Makefile user/jeff/numa/sys/modules/bwn/Makefile user/jeff/numa/sys/modules/i2c/Makefile user/jeff/numa/sys/modules/i2c/iicbus/Makefile user/jeff/numa/sys/netgraph/ng_pppoe.c user/jeff/numa/sys/netgraph/ng_pppoe.h user/jeff/numa/sys/netinet6/nd6_rtr.c user/jeff/numa/sys/netipsec/ipsec.c user/jeff/numa/sys/netipsec/ipsec.h user/jeff/numa/sys/netipsec/xform_ah.c user/jeff/numa/sys/powerpc/aim/aim_machdep.c user/jeff/numa/sys/powerpc/aim/mmu_oea64.c user/jeff/numa/sys/powerpc/aim/moea64_native.c user/jeff/numa/sys/powerpc/aim/slb.c user/jeff/numa/sys/powerpc/booke/booke_machdep.c user/jeff/numa/sys/powerpc/booke/pmap.c user/jeff/numa/sys/powerpc/include/_types.h user/jeff/numa/sys/powerpc/include/pcpu.h user/jeff/numa/sys/powerpc/include/stdarg.h user/jeff/numa/sys/powerpc/ofw/ofw_real.c user/jeff/numa/sys/powerpc/powerpc/genassym.c user/jeff/numa/sys/powerpc/powerpc/trap.c user/jeff/numa/sys/powerpc/ps3/mmu_ps3.c user/jeff/numa/sys/powerpc/pseries/mmu_phyp.c user/jeff/numa/sys/powerpc/pseries/phyp-hvcall.h user/jeff/numa/sys/powerpc/pseries/platform_chrp.c user/jeff/numa/sys/riscv/include/_types.h user/jeff/numa/sys/riscv/include/stdarg.h user/jeff/numa/sys/riscv/riscv/pmap.c user/jeff/numa/sys/security/mac/mac_syscalls.c user/jeff/numa/sys/sparc64/include/_types.h user/jeff/numa/sys/sparc64/include/stdarg.h user/jeff/numa/sys/sparc64/sparc64/pmap.c user/jeff/numa/sys/sys/_types.h user/jeff/numa/sys/sys/aio.h user/jeff/numa/sys/sys/clock.h user/jeff/numa/sys/sys/compressor.h user/jeff/numa/sys/sys/ipc.h user/jeff/numa/sys/sys/kerneldump.h user/jeff/numa/sys/sys/lockstat.h user/jeff/numa/sys/sys/module.h user/jeff/numa/sys/sys/msg.h user/jeff/numa/sys/sys/mutex.h user/jeff/numa/sys/sys/param.h user/jeff/numa/sys/sys/sem.h user/jeff/numa/sys/sys/shm.h user/jeff/numa/sys/sys/vmmeter.h user/jeff/numa/sys/ufs/ffs/ffs_subr.c user/jeff/numa/sys/ufs/ffs/ffs_vfsops.c user/jeff/numa/sys/vm/swap_pager.c user/jeff/numa/sys/vm/vm_fault.c user/jeff/numa/sys/vm/vm_page.c user/jeff/numa/sys/vm/vm_reserv.c user/jeff/numa/sys/x86/include/_types.h user/jeff/numa/sys/x86/include/specialreg.h user/jeff/numa/sys/x86/iommu/intel_gas.c user/jeff/numa/sys/x86/x86/cpu_machdep.c user/jeff/numa/sys/x86/x86/mp_x86.c user/jeff/numa/sys/x86/xen/pv.c user/jeff/numa/sys/x86/xen/xenpv.c Directory Properties: user/jeff/numa/sys/cddl/contrib/opensolaris/ (props changed) user/jeff/numa/sys/contrib/ck/ (props changed) user/jeff/numa/sys/contrib/dev/acpica/ (props changed) user/jeff/numa/sys/contrib/zstd/ (props changed) Modified: user/jeff/numa/sys/amd64/amd64/efirt_machdep.c ============================================================================== --- user/jeff/numa/sys/amd64/amd64/efirt_machdep.c Mon Feb 19 22:09:49 2018 (r329606) +++ user/jeff/numa/sys/amd64/amd64/efirt_machdep.c Mon Feb 19 22:19:44 2018 (r329607) @@ -74,8 +74,7 @@ efi_destroy_1t1_map(void) VM_OBJECT_RLOCK(obj_1t1_pt); TAILQ_FOREACH(m, &obj_1t1_pt->memq, listq) m->wire_count = 0; - VM_CNT_ADD(v_wire_count, - -obj_1t1_pt->resident_page_count); + vm_wire_sub(obj_1t1_pt->resident_page_count); VM_OBJECT_RUNLOCK(obj_1t1_pt); vm_object_deallocate(obj_1t1_pt); } Modified: user/jeff/numa/sys/amd64/amd64/pmap.c ============================================================================== --- user/jeff/numa/sys/amd64/amd64/pmap.c Mon Feb 19 22:09:49 2018 (r329606) +++ user/jeff/numa/sys/amd64/amd64/pmap.c Mon Feb 19 22:19:44 2018 (r329607) @@ -11,17 +11,11 @@ * All rights reserved. * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu> * All rights reserved. - * Copyright (c) 2014-2018 The FreeBSD Foundation - * All rights reserved. * * This code is derived from software contributed to Berkeley by * the Systems Programming Group of the University of Utah Computer * Science Department and William Jolitz of UUNET Technologies Inc. * - * Portions of this software were developed by - * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from - * the FreeBSD Foundation. - * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -54,6 +48,7 @@ */ /*- * Copyright (c) 2003 Networks Associates Technology, Inc. + * Copyright (c) 2014-2018 The FreeBSD Foundation * All rights reserved. * * This software was developed for the FreeBSD Project by Jake Burkholder, @@ -62,6 +57,10 @@ * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA * CHATS research program. * + * Portions of this software were developed by + * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from + * the FreeBSD Foundation. + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -1244,7 +1243,9 @@ pmap_init(void) ("pmap_init: page table page is out of range")); mpte->pindex = pmap_pde_pindex(KERNBASE) + i; mpte->phys_addr = KPTphys + (i << PAGE_SHIFT); + mpte->wire_count = 1; } + vm_wire_add(nkpt); /* * If the kernel is running on a virtual machine, then it must assume @@ -2337,7 +2338,7 @@ pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) pa = VM_PAGE_TO_PHYS(m) | cache_bits; if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) { oldpte |= *pte; - pte_store(pte, pa | pg_g | X86_PG_RW | X86_PG_V); + pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V); } pte++; } @@ -2379,7 +2380,7 @@ pmap_free_zero_pages(struct spglist *free) /* Preserve the page's PG_ZERO setting. */ vm_page_free_toq(m); } - VM_CNT_ADD(v_wire_count, -count); + vm_wire_sub(count); } /* Modified: user/jeff/numa/sys/amd64/conf/NOTES ============================================================================== --- user/jeff/numa/sys/amd64/conf/NOTES Mon Feb 19 22:09:49 2018 (r329606) +++ user/jeff/numa/sys/amd64/conf/NOTES Mon Feb 19 22:19:44 2018 (r329607) @@ -315,6 +315,7 @@ options DRM_DEBUG # Include debug printfs (slow) # Requires the iwn firmware module # ixl: Intel XL710 40Gbe PCIE Ethernet # ixlv: Intel XL710 40Gbe VF PCIE Ethernet +# mthca: Mellanox HCA InfiniBand # mlx4ib: Mellanox ConnectX HCA InfiniBand # mlx4en: Mellanox ConnectX HCA Ethernet # nfe: nVidia nForce MCP on-board Ethernet Networking (BSD open source) @@ -334,6 +335,7 @@ device iwn # Intel 4965/1000/5000/6000 wireless NICs device ixl # Intel XL710 40Gbe PCIE Ethernet options IXL_IW # Enable iWARP Client Interface in ixl(4) device ixlv # Intel XL710 40Gbe VF PCIE Ethernet +device mthca # Mellanox HCA InfiniBand device mlx4 # Shared code module between IB and Ethernet device mlx4ib # Mellanox ConnectX HCA InfiniBand device mlx4en # Mellanox ConnectX HCA Ethernet Modified: user/jeff/numa/sys/amd64/include/asmacros.h ============================================================================== --- user/jeff/numa/sys/amd64/include/asmacros.h Mon Feb 19 22:09:49 2018 (r329606) +++ user/jeff/numa/sys/amd64/include/asmacros.h Mon Feb 19 22:19:44 2018 (r329607) @@ -175,11 +175,11 @@ .endm .macro MOVE_STACKS qw - offset=0 + .L.offset=0 .rept \qw - movq offset(%rsp),%rdx - movq %rdx,offset(%rax) - offset=offset+8 + movq .L.offset(%rsp),%rdx + movq %rdx,.L.offset(%rax) + .L.offset=.L.offset+8 .endr .endm Modified: user/jeff/numa/sys/amd64/include/pcpu.h ============================================================================== --- user/jeff/numa/sys/amd64/include/pcpu.h Mon Feb 19 22:09:49 2018 (r329606) +++ user/jeff/numa/sys/amd64/include/pcpu.h Mon Feb 19 22:19:44 2018 (r329607) @@ -75,7 +75,7 @@ uint32_t pc_pcid_gen; \ uint32_t pc_smp_tlb_done; /* TLB op acknowledgement */ \ uint32_t pc_ibpb_set; \ - char __pad[216] /* be divisor of PAGE_SIZE \ + char __pad[224] /* be divisor of PAGE_SIZE \ after cache alignment */ #define PC_DBREG_CMD_NONE 0 Modified: user/jeff/numa/sys/amd64/linux32/linux32_dummy.c ============================================================================== --- user/jeff/numa/sys/amd64/linux32/linux32_dummy.c Mon Feb 19 22:09:49 2018 (r329606) +++ user/jeff/numa/sys/amd64/linux32/linux32_dummy.c Mon Feb 19 22:19:44 2018 (r329607) @@ -1,5 +1,5 @@ /*- - * SPDX-License-Identifier: BSD-3-Clause + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 1994-1995 Søren Schmidt * All rights reserved. @@ -8,24 +8,22 @@ * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer - * in this position and unchanged. + * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. */ #include <sys/cdefs.h> Modified: user/jeff/numa/sys/amd64/vmm/amd/amdvi_hw.c ============================================================================== --- user/jeff/numa/sys/amd64/vmm/amd/amdvi_hw.c Mon Feb 19 22:09:49 2018 (r329606) +++ user/jeff/numa/sys/amd64/vmm/amd/amdvi_hw.c Mon Feb 19 22:19:44 2018 (r329607) @@ -745,23 +745,8 @@ amdvi_print_pci_cap(device_t dev) softc->pci_cap = cap >> 24; device_printf(softc->dev, "PCI cap 0x%x@0x%x feature:%b\n", cap, off, softc->pci_cap, - "\020\001IOTLB\002HT\003NPCache\004EFR"); + "\20\1IOTLB\2HT\3NPCache\4EFR\5CapExt"); - /* IOMMU spec Rev 2.0, section 3.7.2.1 */ - softc->pci_efr = softc->ctrl->ex_feature; - if (softc->pci_efr) { - device_printf(softc->dev, "PCI extended Feature:%b\n", - (int)softc->pci_efr, - "\020\001PreFSup\002PPRSup\003XTSup\004NXSup\006IASup" - "\007GASup\008HESup\009PCSup"); - device_printf(softc->dev, - "PCI HATS = %d GATS = %d GLXSup = %d, max PASID: 0x%x ", - (int)((softc->pci_efr >> 10) & 0x3), - (int)((softc->pci_efr >> 12) & 0x3), - (int)((softc->pci_efr >> 14) & 0x3), - (int)((softc->pci_efr >> 32) & 0x1F) + 1); - } - return (0); } @@ -1040,7 +1025,7 @@ amdvi_init(void) } if (!amdvi_enable_user && ivhd_count) { printf("bhyve: Found %d AMD-Vi/IOMMU device(s), " - "use hw.vmm.amdvi_enable=1 to enable pass-through.\n", + "use hw.vmm.amdvi.enable=1 to enable pass-through.\n", ivhd_count); return (EINVAL); } @@ -1315,40 +1300,41 @@ static void amdvi_set_dte(struct amdvi_domain *domain, uint16_t devid, bool enable) { struct amdvi_softc *softc; - struct amdvi_dte temp; + struct amdvi_dte* temp; + KASSERT(domain, ("domain is NULL for pci_rid:0x%x\n", devid)); + softc = amdvi_find_iommu(devid); KASSERT(softc, ("softc is NULL for pci_rid:0x%x\n", devid)); - memset(&temp, 0, sizeof(struct amdvi_dte)); + temp = &amdvi_dte[devid]; #ifdef AMDVI_ATS_ENABLE /* If IOMMU and device support IOTLB, enable it. */ if (amdvi_dev_support_iotlb(softc, devid) && softc->iotlb) - temp.iotlb_enable = 1; + temp->iotlb_enable = 1; #endif /* Avoid duplicate I/O faults. */ - temp.sup_second_io_fault = 1; - temp.sup_all_io_fault = amdvi_disable_io_fault; + temp->sup_second_io_fault = 1; + temp->sup_all_io_fault = amdvi_disable_io_fault; - temp.dt_valid = 1; - temp.domain_id = domain->id; + temp->dt_valid = 1; + temp->domain_id = domain->id; if (enable) { if (domain->ptp) { - temp.pt_base = vtophys(domain->ptp) >> 12; - temp.pt_level = amdvi_ptp_level; + temp->pt_base = vtophys(domain->ptp) >> 12; + temp->pt_level = amdvi_ptp_level; } /* * XXX: Page table valid[TV] bit must be set even if host domain * page tables are not enabled. */ - temp.pt_valid = 1; - temp.read_allow = 1; - temp.write_allow = 1; + temp->pt_valid = 1; + temp->read_allow = 1; + temp->write_allow = 1; } - amdvi_dte[devid] = temp; } static void Modified: user/jeff/numa/sys/amd64/vmm/amd/amdvi_priv.h ============================================================================== --- user/jeff/numa/sys/amd64/vmm/amd/amdvi_priv.h Mon Feb 19 22:09:49 2018 (r329606) +++ user/jeff/numa/sys/amd64/vmm/amd/amdvi_priv.h Mon Feb 19 22:19:44 2018 (r329607) @@ -29,6 +29,8 @@ #ifndef _AMDVI_PRIV_H_ #define _AMDVI_PRIV_H_ +#include <contrib/dev/acpica/include/acpi.h> + #define BIT(n) (1ULL << (n)) /* Return value of bits[n:m] where n and (n >= ) m are bit positions. */ #define REG_BITS(x, n, m) (((x) >> (m)) & \ @@ -358,6 +360,7 @@ struct amdvi_domain { struct amdvi_softc { struct amdvi_ctrl *ctrl; /* Control area. */ device_t dev; /* IOMMU device. */ + enum AcpiIvrsType ivhd_type; /* IOMMU IVHD type 0x10/0x11 or 0x40 */ bool iotlb; /* IOTLB supported by IOMMU */ struct amdvi_cmd *cmd; /* Command descriptor area. */ int cmd_max; /* Max number of commands. */ @@ -370,11 +373,11 @@ struct amdvi_softc { int event_rid; /* ACPI various flags. */ uint32_t ivhd_flag; /* ACPI IVHD flag. */ - uint32_t ivhd_efr; /* ACPI v1 Reserved or v2 EFR . */ + uint32_t ivhd_feature; /* ACPI v1 Reserved or v2 attribute. */ + uint64_t ext_feature; /* IVHD EFR */ /* PCI related. */ uint16_t cap_off; /* PCI Capability offset. */ uint8_t pci_cap; /* PCI capability. */ - uint64_t pci_efr; /* PCI EFR for rev2.0 */ uint16_t pci_seg; /* IOMMU PCI domain/segment. */ uint16_t pci_rid; /* PCI BDF of IOMMU */ /* Device range under this IOMMU. */ Modified: user/jeff/numa/sys/amd64/vmm/amd/ivrs_drv.c ============================================================================== --- user/jeff/numa/sys/amd64/vmm/amd/ivrs_drv.c Mon Feb 19 22:09:49 2018 (r329606) +++ user/jeff/numa/sys/amd64/vmm/amd/ivrs_drv.c Mon Feb 19 22:19:44 2018 (r329607) @@ -47,12 +47,16 @@ __FBSDID("$FreeBSD$"); #include "amdvi_priv.h" device_t *ivhd_devs; /* IVHD or AMD-Vi device list. */ -int ivhd_count; /* Number of IVHD or AMD-Vi devices. */ +int ivhd_count; /* Number of IVHD header. */ +/* + * Cached IVHD header list. + * Single entry for each IVHD, filtered the legacy one. + */ +ACPI_IVRS_HARDWARE *ivhd_hdrs[10]; extern int amdvi_ptp_level; /* Page table levels. */ -typedef int (*ivhd_iter_t)(ACPI_IVRS_HEADER * ptr, void *arg); - +typedef int (*ivhd_iter_t)(ACPI_IVRS_HEADER *ptr, void *arg); /* * Iterate IVRS table for IVHD and IVMD device type. */ @@ -107,14 +111,19 @@ ivrs_hdr_iterate_tbl(ivhd_iter_t iter, void *arg) } } -static int +static bool ivrs_is_ivhd(UINT8 type) { - if ((type == ACPI_IVRS_TYPE_HARDWARE) || (type == 0x11) || (type == 0x40)) - return (1); + switch(type) { + case ACPI_IVRS_TYPE_HARDWARE: + case ACPI_IVRS_TYPE_HARDWARE_EXT1: + case ACPI_IVRS_TYPE_HARDWARE_EXT2: + return (true); - return (0); + default: + return (false); + } } /* Count the number of AMD-Vi devices in the system. */ @@ -184,7 +193,7 @@ ivhd_dev_add_entry(struct amdvi_softc *softc, uint32_t * Record device attributes as suggested by BIOS. */ static int -ivhd_dev_parse(ACPI_IVRS_HARDWARE * ivhd, struct amdvi_softc *softc) +ivhd_dev_parse(ACPI_IVRS_HARDWARE* ivhd, struct amdvi_softc *softc) { ACPI_IVRS_DE_HEADER *de; uint8_t *p, *end; @@ -196,11 +205,26 @@ ivhd_dev_parse(ACPI_IVRS_HARDWARE * ivhd, struct amdvi softc->start_dev_rid = ~0; softc->end_dev_rid = 0; - /* - * XXX The following actually depends on Header.Type and - * is only true for 0x10. - */ - p = (uint8_t *)ivhd + sizeof(ACPI_IVRS_HARDWARE); + switch (ivhd->Header.Type) { + case ACPI_IVRS_TYPE_HARDWARE_EXT1: + case ACPI_IVRS_TYPE_HARDWARE_EXT2: + p = (uint8_t *)ivhd + sizeof(ACPI_IVRS_HARDWARE_NEW); + de = (ACPI_IVRS_DE_HEADER *) ((uint8_t *)ivhd + + sizeof(ACPI_IVRS_HARDWARE_NEW)); + break; + + case ACPI_IVRS_TYPE_HARDWARE: + p = (uint8_t *)ivhd + sizeof(ACPI_IVRS_HARDWARE); + de = (ACPI_IVRS_DE_HEADER *) ((uint8_t *)ivhd + + sizeof(ACPI_IVRS_HARDWARE)); + break; + + default: + device_printf(softc->dev, + "unknown type: 0x%x\n", ivhd->Header.Type); + return (-1); + } + end = (uint8_t *)ivhd + ivhd->Header.Length; while (p < end) { @@ -285,14 +309,30 @@ ivhd_dev_parse(ACPI_IVRS_HARDWARE * ivhd, struct amdvi return (0); } +static bool +ivhd_is_newer(ACPI_IVRS_HEADER *old, ACPI_IVRS_HEADER *new) +{ + /* + * Newer IVRS header type take precedence. + */ + if ((old->DeviceId == new->DeviceId) && + (old->Type == ACPI_IVRS_TYPE_HARDWARE) && + ((new->Type == ACPI_IVRS_TYPE_HARDWARE_EXT1) || + (new->Type == ACPI_IVRS_TYPE_HARDWARE_EXT1))) { + return (true); + } + + return (false); +} + static void ivhd_identify(driver_t *driver, device_t parent) { ACPI_TABLE_IVRS *ivrs; ACPI_IVRS_HARDWARE *ivhd; ACPI_STATUS status; - uint32_t info; int i, count = 0; + uint32_t ivrs_ivinfo; if (acpi_disabled("ivhd")) return; @@ -305,25 +345,41 @@ ivhd_identify(driver_t *driver, device_t parent) return; } - info = ivrs->Info; - printf("AMD-Vi IVRS VAsize = %d PAsize = %d GVAsize = %d flags:%b\n", - REG_BITS(info, 21, 15), REG_BITS(info, 14, 8), - REG_BITS(info, 7, 5), REG_BITS(info, 22, 22), - "\020\001HtAtsResv"); + ivrs_ivinfo = ivrs->Info; + printf("AMD-Vi: IVRS Info VAsize = %d PAsize = %d GVAsize = %d" + " flags:%b\n", + REG_BITS(ivrs_ivinfo, 21, 15), REG_BITS(ivrs_ivinfo, 14, 8), + REG_BITS(ivrs_ivinfo, 7, 5), REG_BITS(ivrs_ivinfo, 22, 22), + "\020\001EFRSup"); ivrs_hdr_iterate_tbl(ivhd_count_iter, NULL); if (!ivhd_count) return; - ivhd_devs = malloc(sizeof(device_t) * ivhd_count, M_DEVBUF, - M_WAITOK | M_ZERO); for (i = 0; i < ivhd_count; i++) { ivhd = ivhd_find_by_index(i); - if (ivhd == NULL) { - printf("Can't find IVHD entry%d\n", i); - continue; + KASSERT(ivhd, ("ivhd%d is NULL\n", i)); + ivhd_hdrs[i] = ivhd; + } + + /* + * Scan for presence of legacy and non-legacy device type + * for same AMD-Vi device and override the old one. + */ + for (i = ivhd_count - 1 ; i > 0 ; i--){ + if (ivhd_is_newer(&ivhd_hdrs[i-1]->Header, + &ivhd_hdrs[i]->Header)) { + ivhd_hdrs[i-1] = ivhd_hdrs[i]; + ivhd_count--; } + } + ivhd_devs = malloc(sizeof(device_t) * ivhd_count, M_DEVBUF, + M_WAITOK | M_ZERO); + for (i = 0; i < ivhd_count; i++) { + ivhd = ivhd_hdrs[i]; + KASSERT(ivhd, ("ivhd%d is NULL\n", i)); + /* * Use a high order to ensure that this driver is probed after * the Host-PCI bridge and the root PCI bus. @@ -338,7 +394,7 @@ ivhd_identify(driver_t *driver, device_t parent) if (ivhd_devs[i] == NULL) { ivhd_devs[i] = device_find_child(parent, "ivhd", i); if (ivhd_devs[i] == NULL) { - printf("AMD-Vi: cant find AMD-Vi dev%d\n", i); + printf("AMD-Vi: cant find ivhd%d\n", i); break; } } @@ -354,14 +410,169 @@ ivhd_identify(driver_t *driver, device_t parent) static int ivhd_probe(device_t dev) { + ACPI_IVRS_HARDWARE *ivhd; + int unit; if (acpi_get_handle(dev) != NULL) return (ENXIO); - device_set_desc(dev, "AMD-Vi/IOMMU or ivhd"); + unit = device_get_unit(dev); + KASSERT((unit < ivhd_count), + ("ivhd unit %d > count %d", unit, ivhd_count)); + ivhd = ivhd_hdrs[unit]; + KASSERT(ivhd, ("ivhd is NULL")); + + if (ivhd->Header.Type == ACPI_IVRS_TYPE_HARDWARE) + device_set_desc(dev, "AMD-Vi/IOMMU ivhd"); + else + device_set_desc(dev, "AMD-Vi/IOMMU ivhd with EFR"); + return (BUS_PROBE_NOWILDCARD); } +static void +ivhd_print_flag(device_t dev, enum AcpiIvrsType ivhd_type, uint8_t flag) +{ + /* + * IVHD lgeacy type has two extra high bits in flag which has + * been moved to EFR for non-legacy device. + */ + switch (ivhd_type) { + case ACPI_IVRS_TYPE_HARDWARE: + device_printf(dev, "Flag:%b\n", flag, + "\020" + "\001HtTunEn" + "\002PassPW" + "\003ResPassPW" + "\004Isoc" + "\005IotlbSup" + "\006Coherent" + "\007PreFSup" + "\008PPRSup"); + break; + + case ACPI_IVRS_TYPE_HARDWARE_EXT1: + case ACPI_IVRS_TYPE_HARDWARE_EXT2: + device_printf(dev, "Flag:%b\n", flag, + "\020" + "\001HtTunEn" + "\002PassPW" + "\003ResPassPW" + "\004Isoc" + "\005IotlbSup" + "\006Coherent"); + break; + + default: + device_printf(dev, "Can't decode flag of ivhd type :0x%x\n", + ivhd_type); + break; + } +} + +/* + * Feature in legacy IVHD type(0x10) and attribute in newer type(0x11 and 0x40). + */ +static void +ivhd_print_feature(device_t dev, enum AcpiIvrsType ivhd_type, uint32_t feature) +{ + switch (ivhd_type) { + case ACPI_IVRS_TYPE_HARDWARE: + device_printf(dev, "Features(type:0x%x) HATS = %d GATS = %d" + " MsiNumPPR = %d PNBanks= %d PNCounters= %d\n", + ivhd_type, + REG_BITS(feature, 31, 30), + REG_BITS(feature, 29, 28), + REG_BITS(feature, 27, 23), + REG_BITS(feature, 22, 17), + REG_BITS(feature, 16, 13)); + device_printf(dev, "max PASID = %d GLXSup = %d Feature:%b\n", + REG_BITS(feature, 12, 8), + REG_BITS(feature, 4, 3), + feature, + "\020" + "\002NXSup" + "\003GTSup" + "\004<b4>" + "\005IASup" + "\006GASup" + "\007HESup"); + break; + + /* Fewer features or attributes are reported in non-legacy type. */ + case ACPI_IVRS_TYPE_HARDWARE_EXT1: + case ACPI_IVRS_TYPE_HARDWARE_EXT2: + device_printf(dev, "Features(type:0x%x) MsiNumPPR = %d" + " PNBanks= %d PNCounters= %d\n", + ivhd_type, + REG_BITS(feature, 27, 23), + REG_BITS(feature, 22, 17), + REG_BITS(feature, 16, 13)); + break; + + default: /* Other ivhd type features are not decoded. */ + device_printf(dev, "Can't decode ivhd type :0x%x\n", ivhd_type); + } +} + +/* Print extended features of IOMMU. */ +static void +ivhd_print_ext_feature(device_t dev, uint64_t ext_feature) +{ + uint32_t ext_low, ext_high; + + if (!ext_feature) + return; + + ext_low = ext_feature; + device_printf(dev, "Extended features[31:0]:%b " + "HATS = 0x%x GATS = 0x%x " + "GLXSup = 0x%x SmiFSup = 0x%x SmiFRC = 0x%x " + "GAMSup = 0x%x DualPortLogSup = 0x%x DualEventLogSup = 0x%x\n", + (int)ext_low, + "\020" + "\001PreFSup" + "\002PPRSup" + "\003<b2>" + "\004NXSup" + "\005GTSup" + "\006<b5>" + "\007IASup" + "\008GASup" + "\009HESup" + "\010PCSup", + REG_BITS(ext_low, 11, 10), + REG_BITS(ext_low, 13, 12), + REG_BITS(ext_low, 15, 14), + REG_BITS(ext_low, 17, 16), + REG_BITS(ext_low, 20, 18), + REG_BITS(ext_low, 23, 21), + REG_BITS(ext_low, 25, 24), + REG_BITS(ext_low, 29, 28)); + + ext_high = ext_feature >> 32; + device_printf(dev, "Extended features[62:32]:%b " + "Max PASID: 0x%x DevTblSegSup = 0x%x " + "MarcSup = 0x%x\n", + (int)(ext_high), + "\020" + "\006USSup" + "\009PprOvrflwEarlySup" + "\010PPRAutoRspSup" + "\013BlKStopMrkSup" + "\014PerfOptSup" + "\015MsiCapMmioSup" + "\017GIOSup" + "\018HASup" + "\019EPHSup" + "\020AttrFWSup" + "\021HDSup" + "\023InvIotlbSup", + REG_BITS(ext_high, 5, 0), + REG_BITS(ext_high, 8, 7), + REG_BITS(ext_high, 11, 10)); +} + static int ivhd_print_cap(struct amdvi_softc *softc, ACPI_IVRS_HARDWARE * ivhd) { @@ -369,41 +580,23 @@ ivhd_print_cap(struct amdvi_softc *softc, ACPI_IVRS_HA int max_ptp_level; dev = softc->dev; - device_printf(dev, "Flag:%b\n", softc->ivhd_flag, - "\020\001HtTunEn\002PassPW\003ResPassPW\004Isoc\005IotlbSup" - "\006Coherent\007PreFSup\008PPRSup"); - /* - * If no extended feature[EFR], its rev1 with maximum paging level as 7. - */ + + ivhd_print_flag(dev, softc->ivhd_type, softc->ivhd_flag); + ivhd_print_feature(dev, softc->ivhd_type, softc->ivhd_feature); + ivhd_print_ext_feature(dev, softc->ext_feature); max_ptp_level = 7; - if (softc->ivhd_efr) { - device_printf(dev, "EFR HATS = %d GATS = %d GLXSup = %d " - "MsiNumPr = %d PNBanks= %d PNCounters= %d\n" - "max PASID = %d EFR: %b \n", - REG_BITS(softc->ivhd_efr, 31, 30), - REG_BITS(softc->ivhd_efr, 29, 28), - REG_BITS(softc->ivhd_efr, 4, 3), - REG_BITS(softc->ivhd_efr, 27, 23), - REG_BITS(softc->ivhd_efr, 22, 17), - REG_BITS(softc->ivhd_efr, 16, 13), - REG_BITS(softc->ivhd_efr, 12, 8), - softc->ivhd_efr, "\020\001XTSup\002NXSup\003GTSup\005IASup" - "\006GASup\007HESup\008PPRSup"); - - max_ptp_level = REG_BITS(softc->ivhd_efr, 31, 30) + 4; - } - /* Make sure device support minimum page level as requested by user. */ if (max_ptp_level < amdvi_ptp_level) { - device_printf(dev, "Insufficient PTP level:%d\n", - max_ptp_level); + device_printf(dev, "insufficient PTP level:%d\n", + max_ptp_level); return (EINVAL); + } else { + device_printf(softc->dev, "supported paging level:%d, will use only: %d\n", + max_ptp_level, amdvi_ptp_level); } - device_printf(softc->dev, "max supported paging level:%d restricting to: %d\n", - max_ptp_level, amdvi_ptp_level); - device_printf(softc->dev, "device supported range " - "[0x%x - 0x%x]\n", softc->start_dev_rid, softc->end_dev_rid); + device_printf(softc->dev, "device range: 0x%x - 0x%x\n", + softc->start_dev_rid, softc->end_dev_rid); return (0); } @@ -412,25 +605,32 @@ static int ivhd_attach(device_t dev) { ACPI_IVRS_HARDWARE *ivhd; + ACPI_IVRS_HARDWARE_NEW *ivhd1; struct amdvi_softc *softc; int status, unit; unit = device_get_unit(dev); + KASSERT((unit < ivhd_count), + ("ivhd unit %d > count %d", unit, ivhd_count)); /* Make sure its same device for which attach is called. */ - if (ivhd_devs[unit] != dev) - panic("Not same device old %p new %p", ivhd_devs[unit], dev); + KASSERT((ivhd_devs[unit] == dev), + ("Not same device old %p new %p", ivhd_devs[unit], dev)); softc = device_get_softc(dev); softc->dev = dev; - ivhd = ivhd_find_by_index(unit); - if (ivhd == NULL) - return (EINVAL); + ivhd = ivhd_hdrs[unit]; + KASSERT(ivhd, ("ivhd is NULL")); + softc->ivhd_type = ivhd->Header.Type; softc->pci_seg = ivhd->PciSegmentGroup; softc->pci_rid = ivhd->Header.DeviceId; softc->ivhd_flag = ivhd->Header.Flags; - softc->ivhd_efr = ivhd->Reserved; /* + * On lgeacy IVHD type(0x10), it is documented as feature + * but in newer type it is attribute. + */ + softc->ivhd_feature = ivhd->Reserved; + /* * PCI capability has more capabilities that are not part of IVRS. */ softc->cap_off = ivhd->CapabilityOffset; @@ -439,6 +639,15 @@ ivhd_attach(device_t dev) /* IVHD Info bit[4:0] is event MSI/X number. */ softc->event_msix = ivhd->Info & 0x1F; #endif + switch (ivhd->Header.Type) { + case ACPI_IVRS_TYPE_HARDWARE_EXT1: + case ACPI_IVRS_TYPE_HARDWARE_EXT2: + ivhd1 = (ACPI_IVRS_HARDWARE_NEW *)ivhd; + softc->ext_feature = ivhd1->ExtFR; + break; + + } + softc->ctrl = (struct amdvi_ctrl *) PHYS_TO_DMAP(ivhd->BaseAddress); status = ivhd_dev_parse(ivhd, softc); if (status != 0) { Modified: user/jeff/numa/sys/amd64/vmm/amd/svm.c ============================================================================== --- user/jeff/numa/sys/amd64/vmm/amd/svm.c Mon Feb 19 22:09:49 2018 (r329606) +++ user/jeff/numa/sys/amd64/vmm/amd/svm.c Mon Feb 19 22:19:44 2018 (r329607) @@ -969,6 +969,7 @@ svm_save_intinfo(struct svm_softc *svm_sc, int vcpu) vm_exit_intinfo(svm_sc->vm, vcpu, intinfo); } +#ifdef INVARIANTS static __inline int vintr_intercept_enabled(struct svm_softc *sc, int vcpu) { @@ -976,6 +977,7 @@ vintr_intercept_enabled(struct svm_softc *sc, int vcpu return (svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_VINTR)); } +#endif static __inline void enable_intr_window_exiting(struct svm_softc *sc, int vcpu) Modified: user/jeff/numa/sys/amd64/vmm/amd/svm_support.S ============================================================================== --- user/jeff/numa/sys/amd64/vmm/amd/svm_support.S Mon Feb 19 22:09:49 2018 (r329606) +++ user/jeff/numa/sys/amd64/vmm/amd/svm_support.S Mon Feb 19 22:19:44 2018 (r329607) @@ -113,6 +113,23 @@ ENTRY(svm_launch) movq %rdi, SCTX_RDI(%rax) movq %rsi, SCTX_RSI(%rax) + /* + * To prevent malicious branch target predictions from + * affecting the host, overwrite all entries in the RSB upon + * exiting a guest. + */ + mov $16, %ecx /* 16 iterations, two calls per loop */ + mov %rsp, %rax +0: call 2f /* create an RSB entry. */ +1: pause + call 1b /* capture rogue speculation. */ +2: call 2f /* create an RSB entry. */ +1: pause + call 1b /* capture rogue speculation. */ +2: sub $1, %ecx + jnz 0b + mov %rax, %rsp + /* Restore host state */ pop %r15 pop %r14 Modified: user/jeff/numa/sys/amd64/vmm/intel/vmcs.c ============================================================================== --- user/jeff/numa/sys/amd64/vmm/intel/vmcs.c Mon Feb 19 22:09:49 2018 (r329606) +++ user/jeff/numa/sys/amd64/vmm/intel/vmcs.c Mon Feb 19 22:19:44 2018 (r329607) @@ -34,6 +34,7 @@ __FBSDID("$FreeBSD$"); #include <sys/param.h> +#include <sys/sysctl.h> #include <sys/systm.h> #include <sys/pcpu.h> @@ -52,6 +53,12 @@ __FBSDID("$FreeBSD$"); #include <ddb/ddb.h> #endif +SYSCTL_DECL(_hw_vmm_vmx); + +static int no_flush_rsb; +SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, no_flush_rsb, CTLFLAG_RW, + &no_flush_rsb, 0, "Do not flush RSB upon vmexit"); + static uint64_t vmcs_fix_regval(uint32_t encoding, uint64_t val) { @@ -403,8 +410,15 @@ vmcs_init(struct vmcs *vmcs) goto done; /* instruction pointer */ - if ((error = vmwrite(VMCS_HOST_RIP, (u_long)vmx_exit_guest)) != 0) - goto done; + if (no_flush_rsb) { + if ((error = vmwrite(VMCS_HOST_RIP, + (u_long)vmx_exit_guest)) != 0) + goto done; + } else { + if ((error = vmwrite(VMCS_HOST_RIP, + (u_long)vmx_exit_guest_flush_rsb)) != 0) + goto done; + } /* link pointer */ if ((error = vmwrite(VMCS_LINK_POINTER, ~0)) != 0) Modified: user/jeff/numa/sys/amd64/vmm/intel/vmx.h ============================================================================== --- user/jeff/numa/sys/amd64/vmm/intel/vmx.h Mon Feb 19 22:09:49 2018 (r329606) +++ user/jeff/numa/sys/amd64/vmm/intel/vmx.h Mon Feb 19 22:19:44 2018 (r329607) @@ -150,5 +150,6 @@ u_long vmx_fix_cr4(u_long cr4); int vmx_set_tsc_offset(struct vmx *vmx, int vcpu, uint64_t offset); extern char vmx_exit_guest[]; +extern char vmx_exit_guest_flush_rsb[]; #endif Modified: user/jeff/numa/sys/amd64/vmm/intel/vmx_support.S ============================================================================== --- user/jeff/numa/sys/amd64/vmm/intel/vmx_support.S Mon Feb 19 22:09:49 2018 (r329606) +++ user/jeff/numa/sys/amd64/vmm/intel/vmx_support.S Mon Feb 19 22:19:44 2018 (r329607) @@ -42,6 +42,29 @@ #define VLEAVE pop %rbp /* + * Save the guest context. + */ +#define VMX_GUEST_SAVE \ + movq %rdi,VMXCTX_GUEST_RDI(%rsp); \ + movq %rsi,VMXCTX_GUEST_RSI(%rsp); \ + movq %rdx,VMXCTX_GUEST_RDX(%rsp); \ + movq %rcx,VMXCTX_GUEST_RCX(%rsp); \ + movq %r8,VMXCTX_GUEST_R8(%rsp); \ + movq %r9,VMXCTX_GUEST_R9(%rsp); \ + movq %rax,VMXCTX_GUEST_RAX(%rsp); \ + movq %rbx,VMXCTX_GUEST_RBX(%rsp); \ + movq %rbp,VMXCTX_GUEST_RBP(%rsp); \ + movq %r10,VMXCTX_GUEST_R10(%rsp); \ + movq %r11,VMXCTX_GUEST_R11(%rsp); \ + movq %r12,VMXCTX_GUEST_R12(%rsp); \ + movq %r13,VMXCTX_GUEST_R13(%rsp); \ + movq %r14,VMXCTX_GUEST_R14(%rsp); \ + movq %r15,VMXCTX_GUEST_R15(%rsp); \ + movq %cr2,%rdi; \ + movq %rdi,VMXCTX_GUEST_CR2(%rsp); \ + movq %rsp,%rdi; + +/* * Assumes that %rdi holds a pointer to the 'vmxctx'. * * On "return" all registers are updated to reflect guest state. The two @@ -211,31 +234,55 @@ inst_error: * The VMCS-restored %rsp points to the struct vmxctx */ ALIGN_TEXT - .globl vmx_exit_guest -vmx_exit_guest: + .globl vmx_exit_guest_flush_rsb +vmx_exit_guest_flush_rsb: /* * Save guest state that is not automatically saved in the vmcs. */ - movq %rdi,VMXCTX_GUEST_RDI(%rsp) - movq %rsi,VMXCTX_GUEST_RSI(%rsp) - movq %rdx,VMXCTX_GUEST_RDX(%rsp) - movq %rcx,VMXCTX_GUEST_RCX(%rsp) - movq %r8,VMXCTX_GUEST_R8(%rsp) - movq %r9,VMXCTX_GUEST_R9(%rsp) - movq %rax,VMXCTX_GUEST_RAX(%rsp) - movq %rbx,VMXCTX_GUEST_RBX(%rsp) - movq %rbp,VMXCTX_GUEST_RBP(%rsp) - movq %r10,VMXCTX_GUEST_R10(%rsp) - movq %r11,VMXCTX_GUEST_R11(%rsp) - movq %r12,VMXCTX_GUEST_R12(%rsp) - movq %r13,VMXCTX_GUEST_R13(%rsp) - movq %r14,VMXCTX_GUEST_R14(%rsp) - movq %r15,VMXCTX_GUEST_R15(%rsp) + VMX_GUEST_SAVE - movq %cr2,%rdi - movq %rdi,VMXCTX_GUEST_CR2(%rsp) + /* + * Deactivate guest pmap from this cpu. + */ + movq VMXCTX_PMAP(%rdi), %r11 + movl PCPU(CPUID), %r10d + LK btrl %r10d, PM_ACTIVE(%r11) - movq %rsp,%rdi + VMX_HOST_RESTORE + + VMX_GUEST_CLOBBER + + /* + * To prevent malicious branch target predictions from + * affecting the host, overwrite all entries in the RSB upon + * exiting a guest. + */ + mov $16, %ecx /* 16 iterations, two calls per loop */ + mov %rsp, %rax +0: call 2f /* create an RSB entry. */ +1: pause + call 1b /* capture rogue speculation. */ +2: call 2f /* create an RSB entry. */ +1: pause + call 1b /* capture rogue speculation. */ +2: sub $1, %ecx + jnz 0b + mov %rax, %rsp + + /* + * This will return to the caller of 'vmx_enter_guest()' with a return + * value of VMX_GUEST_VMEXIT. + */ + movl $VMX_GUEST_VMEXIT, %eax + VLEAVE + ret + + .globl vmx_exit_guest +vmx_exit_guest: + /* + * Save guest state that is not automatically saved in the vmcs. + */ + VMX_GUEST_SAVE /* * Deactivate guest pmap from this cpu. Modified: user/jeff/numa/sys/arm/allwinner/aw_mmc.c ============================================================================== --- user/jeff/numa/sys/arm/allwinner/aw_mmc.c Mon Feb 19 22:09:49 2018 (r329606) +++ user/jeff/numa/sys/arm/allwinner/aw_mmc.c Mon Feb 19 22:19:44 2018 (r329607) @@ -117,6 +117,7 @@ struct aw_mmc_softc { int32_t aw_vdd; regulator_t aw_reg_vmmc; regulator_t aw_reg_vqmmc; + unsigned int aw_clock; /* Fields required for DMA access. */ bus_addr_t aw_dma_desc_phys; @@ -939,8 +940,8 @@ aw_mmc_update_ios(device_t bus, device_t child) reg &= ~AW_MMC_CTRL_DDR_MOD_SEL; AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); - if (ios->clock) { - clock = ios->clock; + if (ios->clock && ios->clock != sc->aw_clock) { + sc->aw_clock = clock = ios->clock; /* Disable clock */ error = aw_mmc_update_clock(sc, 0); Modified: user/jeff/numa/sys/arm/arm/gic_acpi.c ============================================================================== --- user/jeff/numa/sys/arm/arm/gic_acpi.c Mon Feb 19 22:09:49 2018 (r329606) +++ user/jeff/numa/sys/arm/arm/gic_acpi.c Mon Feb 19 22:19:44 2018 (r329607) @@ -342,5 +342,5 @@ DEFINE_CLASS_1(gicv2m, arm_gicv2m_acpi_driver, arm_gic static devclass_t arm_gicv2m_acpi_devclass; -EARLY_DRIVER_MODULE(gicv2m, gic, arm_gicv2m_acpi_driver, +EARLY_DRIVER_MODULE(gicv2m_acpi, gic, arm_gicv2m_acpi_driver, arm_gicv2m_acpi_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); Modified: user/jeff/numa/sys/arm/arm/pmap-v6.c ============================================================================== --- user/jeff/numa/sys/arm/arm/pmap-v6.c Mon Feb 19 22:09:49 2018 (r329606) +++ user/jeff/numa/sys/arm/arm/pmap-v6.c Mon Feb 19 22:19:44 2018 (r329607) @@ -2639,7 +2639,7 @@ pmap_unwire_pt2pg(pmap_t pmap, vm_offset_t va, vm_page * down is begun. */ wmb(); - VM_CNT_ADD(v_wire_count, -1); + vm_wire_sub(1); } /* @@ -2946,7 +2946,7 @@ out: SLIST_REMOVE_HEAD(&free, plinks.s.ss); *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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