Date: Sun, 20 Jan 2002 19:57:25 -0700 (MST) From: "M. Warner Losh" <imp@village.org> To: peter.jeremy@alcatel.com.au Cc: wollman@khavrinen.lcs.mit.edu, arch@FreeBSD.ORG Subject: Re: 64 bit counters again Message-ID: <20020120.195725.87764038.imp@village.org> In-Reply-To: <20020121125522.G72285@gsmx07.alcatel.com.au> References: <20020121082826.Z72285@gsmx07.alcatel.com.au> <200201202251.g0KMpq032842@khavrinen.lcs.mit.edu> <20020121125522.G72285@gsmx07.alcatel.com.au>
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In message: <20020121125522.G72285@gsmx07.alcatel.com.au> Peter Jeremy <peter.jeremy@alcatel.com.au> writes: : >Actually, the SPARC would be similar to the Intel. I think only Alpha : >and MIPS implemented the LL/SC version of this primitive. Not all MIPS processors have LL/SC. Vr41xx lack this, for example. However, there are no SMP Vr41xx systems, and I don't think any can be made due to all that cache coherency and interprocessor locking crap being removed :-) Warner To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-arch" in the body of the message
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