Date: Fri, 29 Mar 2013 16:40:53 GMT From: Robert Watson <rwatson@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 227226 for review Message-ID: <201303291640.r2TGerh9045588@skunkworks.freebsd.org>
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http://p4web.freebsd.org/@@227226?ac=10 Change 227226 by rwatson@rwatson_zenith_cl_cam_ac_uk on 2013/03/29 16:40:14 Modify libstand's setjmp/longjmp to use wrapper macros so that they are 64-bit MIPS-happy, rather than just 32-bit MIPS happy. For now, and just in the FreeBSD/beri branch, ifdef out FP register manipulation, as we don't have a floating-point coprocessor. Affected files ... .. //depot/projects/ctsrd/beribsd/src/lib/libstand/mips/_setjmp.S#3 edit Differences ... ==== //depot/projects/ctsrd/beribsd/src/lib/libstand/mips/_setjmp.S#3 (text+ko) ==== @@ -60,32 +60,35 @@ LEAF(_setjmp) .set noreorder li v0, 0xACEDBADE # sigcontext magic number - sw ra, (2 * 4)(a0) # sc_pc = return address - sw v0, (3 * 4)(a0) # saved in sc_regs[0] - sw s0, ((S0 + 3) * 4)(a0) - sw s1, ((S1 + 3) * 4)(a0) - sw s2, ((S2 + 3) * 4)(a0) - sw s3, ((S3 + 3) * 4)(a0) - sw s4, ((S4 + 3) * 4)(a0) - sw s5, ((S5 + 3) * 4)(a0) - sw s6, ((S6 + 3) * 4)(a0) - sw s7, ((S7 + 3) * 4)(a0) - sw sp, ((SP + 3) * 4)(a0) - sw s8, ((S8 + 3) * 4)(a0) + REG_S ra, (2 * SZREG)(a0) # sc_pc = return address + REG_S v0, (3 * SZREG)(a0) # saved in sc_regs[0] + REG_S s0, ((S0 + 3) * SZREG)(a0) + REG_S s1, ((S1 + 3) * SZREG)(a0) + REG_S s2, ((S2 + 3) * SZREG)(a0) + REG_S s3, ((S3 + 3) * SZREG)(a0) + REG_S s4, ((S4 + 3) * SZREG)(a0) + REG_S s5, ((S5 + 3) * SZREG)(a0) + REG_S s6, ((S6 + 3) * SZREG)(a0) + REG_S s7, ((S7 + 3) * SZREG)(a0) + REG_S sp, ((SP + 3) * SZREG)(a0) + REG_S s8, ((S8 + 3) * SZREG)(a0) +/* XXXRW: Don't try to save/restore FP in libstand. */ +#if 0 cfc1 v0, $31 # too bad cant check if FP used - swc1 $f20, ((20 + 38) * 4)(a0) - swc1 $f21, ((21 + 38) * 4)(a0) - swc1 $f22, ((22 + 38) * 4)(a0) - swc1 $f23, ((23 + 38) * 4)(a0) - swc1 $f24, ((24 + 38) * 4)(a0) - swc1 $f25, ((25 + 38) * 4)(a0) - swc1 $f26, ((26 + 38) * 4)(a0) - swc1 $f27, ((27 + 38) * 4)(a0) - swc1 $f28, ((28 + 38) * 4)(a0) - swc1 $f29, ((29 + 38) * 4)(a0) - swc1 $f30, ((30 + 38) * 4)(a0) - swc1 $f31, ((31 + 38) * 4)(a0) - sw v0, ((32 + 38) * 4)(a0) + FP_S $f20, ((20 + 38) * SZREG)(a0) + FP_S $f21, ((21 + 38) * SZREG)(a0) + FP_S $f22, ((22 + 38) * SZREG)(a0) + FP_S $f23, ((23 + 38) * SZREG)(a0) + FP_S $f24, ((24 + 38) * SZREG)(a0) + FP_S $f25, ((25 + 38) * SZREG)(a0) + FP_S $f26, ((26 + 38) * SZREG)(a0) + FP_S $f27, ((27 + 38) * SZREG)(a0) + FP_S $f28, ((28 + 38) * SZREG)(a0) + FP_S $f29, ((29 + 38) * SZREG)(a0) + FP_S $f30, ((30 + 38) * SZREG)(a0) + FP_S $f31, ((31 + 38) * SZREG)(a0) +#endif + REG_S v0, ((32 + 38) * SZREG)(a0) j ra move v0, zero END(_setjmp) @@ -96,38 +99,41 @@ .cprestore 16 #endif .set noreorder - lw v0, (3 * 4)(a0) # get magic number - lw ra, (2 * 4)(a0) + REG_L v0, (3 * SZREG)(a0) # get magic number + REG_L ra, (2 * SZREG)(a0) bne v0, 0xACEDBADE, botch # jump if error addu sp, sp, 32 # does not matter, sanity - lw s0, ((S0 + 3) * 4)(a0) - lw s1, ((S1 + 3) * 4)(a0) - lw s2, ((S2 + 3) * 4)(a0) - lw s3, ((S3 + 3) * 4)(a0) - lw s4, ((S4 + 3) * 4)(a0) - lw s5, ((S5 + 3) * 4)(a0) - lw s6, ((S6 + 3) * 4)(a0) - lw s7, ((S7 + 3) * 4)(a0) - lw v0, ((32 + 38) * 4)(a0) # get fpu status - lw sp, ((SP + 3) * 4)(a0) - lw s8, ((S8 + 3) * 4)(a0) + REG_L s0, ((S0 + 3) * SZREG)(a0) + REG_L s1, ((S1 + 3) * SZREG)(a0) + REG_L s2, ((S2 + 3) * SZREG)(a0) + REG_L s3, ((S3 + 3) * SZREG)(a0) + REG_L s4, ((S4 + 3) * SZREG)(a0) + REG_L s5, ((S5 + 3) * SZREG)(a0) + REG_L s6, ((S6 + 3) * SZREG)(a0) + REG_L s7, ((S7 + 3) * SZREG)(a0) + REG_L v0, ((32 + 38) * SZREG)(a0) # get fpu status + REG_L sp, ((SP + 3) * SZREG)(a0) + REG_L s8, ((S8 + 3) * SZREG)(a0) +/* XXXRW: Don't try to save/restore FP in libstand. */ +#if 0 /* Octeon does not have an FPU */ #if !defined(_MIPS_ARCH_OCTEON) ctc1 v0, $31 - lwc1 $f20, ((20 + 38) * 4)(a0) - lwc1 $f21, ((21 + 38) * 4)(a0) - lwc1 $f22, ((22 + 38) * 4)(a0) - lwc1 $f23, ((23 + 38) * 4)(a0) - lwc1 $f24, ((24 + 38) * 4)(a0) - lwc1 $f25, ((25 + 38) * 4)(a0) - lwc1 $f26, ((26 + 38) * 4)(a0) - lwc1 $f27, ((27 + 38) * 4)(a0) - lwc1 $f28, ((28 + 38) * 4)(a0) - lwc1 $f29, ((29 + 38) * 4)(a0) - lwc1 $f30, ((30 + 38) * 4)(a0) - lwc1 $f31, ((31 + 38) * 4)(a0) + FP_L $f20, ((20 + 38) * SZREG)(a0) + FP_L $f21, ((21 + 38) * SZREG)(a0) + FP_L $f22, ((22 + 38) * SZREG)(a0) + FP_L $f23, ((23 + 38) * SZREG)(a0) + FP_L $f24, ((24 + 38) * SZREG)(a0) + FP_L $f25, ((25 + 38) * SZREG)(a0) + FP_L $f26, ((26 + 38) * SZREG)(a0) + FP_L $f27, ((27 + 38) * SZREG)(a0) + FP_L $f28, ((28 + 38) * SZREG)(a0) + FP_L $f29, ((29 + 38) * SZREG)(a0) + FP_L $f30, ((30 + 38) * SZREG)(a0) + FP_L $f31, ((31 + 38) * SZREG)(a0) #endif /* _MIPS_ARCH_OCTEON */ +#endif j ra move v0, a1
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