Date: Fri, 28 Nov 1997 21:13:17 GMT From: jak@cetlink.net (John Kelly) To: Bruce Evans <bde@zeta.org.au> Cc: hackers@freebsd.org Subject: Re: 650 UART, SIO driver, 8259 PIC Message-ID: <347f2aea.22335910@mail.cetlink.net> In-Reply-To: <199711281810.FAA09194@godzilla.zeta.org.au> References: <199711281810.FAA09194@godzilla.zeta.org.au>
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On Sat, 29 Nov 1997 05:10:56 +1100, Bruce Evans <bde@zeta.org.au> wrote: >According to the diagram in the Intel data sheet, and my experiments, >the IRR follows a signal from the edge latch until the edge latch is >cleared - it reads as 0. > >> 9 The INT latch is cleared -- so the INT output is set >> inactive. > >According to the diagram in the Intel data sheet, and my experiments, >the edge latch isn't cleared until the external interrupt goes away. > >> 10 B3 of the IRR is set to 0 (IRR is unfrozen and B3 of >> ESR is zero). I don't know what experiment you performed, but using a volt meter and some ISR test code with dummy loops long enough to watch the voltage change, I've proven that a down/up transition on the external IRQ line before EOI will produce a new interrupt when exiting the ISR, assuming the external IRQ line is still high upon exit (which it would be). >>other useful work, by clearing the INT output of the last UART before >>any of the previously drained UARTs can raise their INT output again, >>you will have at least one down/up transition on the IRQ line. If you > >That would be a pessimization. It requires _two_ extra outputs per >port (one to mess up the INT enable and one to restore it). That's not what I meant. :-( I'm not going to poke the UART twice to toggle interrupt enable. The act of draining the FIFO will cause each UART to pull its INT output (pin 30 on a 40-pin DIP) to ground. In the case of an 8-port shared interrupt card, at the instant the last UART is drained below its FIFO trigger level, all eight INT output pins will be at ground. If one of the eight is subsequently refilled to receive trigger level it will raise its INT output high again, but that's OK because since all eight were at ground, you have a low to high transition and a new interrupt after exiting the ISR. So far, I have been discussing only the problems associated with receive data, completely ignoring the complications of transmitter interrupts. But I've been trying to accurately establish the facts of the simple case first. John
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