Date: Mon, 10 Aug 2015 18:38:00 GMT From: mihai@FreeBSD.org To: svn-soc-all@FreeBSD.org Subject: socsvn commit: r289530 - in soc2015/mihai/bhyve-on-arm-head/sys/arm: arm include Message-ID: <201508101838.t7AIc06J067595@socsvn.freebsd.org>
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Author: mihai Date: Mon Aug 10 18:38:00 2015 New Revision: 289530 URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=289530 Log: sys: arm: arm: gic.c: move defines in header to be used by other infrastructures Added: soc2015/mihai/bhyve-on-arm-head/sys/arm/include/gic.h Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/arm/gic.c Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/arm/gic.c ============================================================================== --- soc2015/mihai/bhyve-on-arm-head/sys/arm/arm/gic.c Mon Aug 10 18:37:28 2015 (r289529) +++ soc2015/mihai/bhyve-on-arm-head/sys/arm/arm/gic.c Mon Aug 10 18:38:00 2015 (r289530) @@ -49,88 +49,25 @@ #include <machine/bus.h> #include <machine/intr.h> #include <machine/smp.h> +#include <machine/gic.h> #include <dev/fdt/fdt_common.h> #include <dev/ofw/openfirm.h> #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> -/* We are using GICv2 register naming */ - -/* Distributor Registers */ -#define GICD_CTLR 0x000 /* v1 ICDDCR */ -#define GICD_TYPER 0x004 /* v1 ICDICTR */ -#define GICD_IIDR 0x008 /* v1 ICDIIDR */ -#define GICD_IGROUPR(n) (0x0080 + ((n) * 4)) /* v1 ICDISER */ -#define GICD_ISENABLER(n) (0x0100 + ((n) * 4)) /* v1 ICDISER */ -#define GICD_ICENABLER(n) (0x0180 + ((n) * 4)) /* v1 ICDICER */ -#define GICD_ISPENDR(n) (0x0200 + ((n) * 4)) /* v1 ICDISPR */ -#define GICD_ICPENDR(n) (0x0280 + ((n) * 4)) /* v1 ICDICPR */ -#define GICD_ICACTIVER(n) (0x0380 + ((n) * 4)) /* v1 ICDABR */ -#define GICD_IPRIORITYR(n) (0x0400 + ((n) * 4)) /* v1 ICDIPR */ -#define GICD_ITARGETSR(n) (0x0800 + ((n) * 4)) /* v1 ICDIPTR */ -#define GICD_ICFGR(n) (0x0C00 + ((n) * 4)) /* v1 ICDICFR */ -#define GICD_SGIR(n) (0x0F00 + ((n) * 4)) /* v1 ICDSGIR */ - -/* CPU Registers */ -#define GICC_CTLR 0x0000 /* v1 ICCICR */ -#define GICC_PMR 0x0004 /* v1 ICCPMR */ -#define GICC_BPR 0x0008 /* v1 ICCBPR */ -#define GICC_IAR 0x000C /* v1 ICCIAR */ -#define GICC_EOIR 0x0010 /* v1 ICCEOIR */ -#define GICC_RPR 0x0014 /* v1 ICCRPR */ -#define GICC_HPPIR 0x0018 /* v1 ICCHPIR */ -#define GICC_ABPR 0x001C /* v1 ICCABPR */ -#define GICC_IIDR 0x00FC /* v1 ICCIIDR*/ - -#define GIC_FIRST_IPI 0 /* Irqs 0-15 are SGIs/IPIs. */ -#define GIC_LAST_IPI 15 -#define GIC_FIRST_PPI 16 /* Irqs 16-31 are private (per */ -#define GIC_LAST_PPI 31 /* core) peripheral interrupts. */ -#define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */ - -/* First bit is a polarity bit (0 - low, 1 - high) */ -#define GICD_ICFGR_POL_LOW (0 << 0) -#define GICD_ICFGR_POL_HIGH (1 << 0) -#define GICD_ICFGR_POL_MASK 0x1 -/* Second bit is a trigger bit (0 - level, 1 - edge) */ -#define GICD_ICFGR_TRIG_LVL (0 << 1) -#define GICD_ICFGR_TRIG_EDGE (1 << 1) -#define GICD_ICFGR_TRIG_MASK 0x2 - -#ifndef GIC_DEFAULT_ICFGR_INIT -#define GIC_DEFAULT_ICFGR_INIT 0x00000000 -#endif - -struct arm_gic_softc { - device_t gic_dev; - struct resource * gic_res[3]; - bus_space_tag_t gic_c_bst; - bus_space_tag_t gic_d_bst; - bus_space_handle_t gic_c_bsh; - bus_space_handle_t gic_d_bsh; - uint8_t ver; - struct mtx mutex; - uint32_t nirqs; -}; - static struct resource_spec arm_gic_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Distributor registers */ { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* CPU Interrupt Intf. registers */ +#ifdef VMM_ARM_VGIC + { SYS_RES_MEMORY, 2, RF_ACTIVE }, /* Virtual Interface Control */ + { SYS_RES_MEMORY, 3, RF_ACTIVE }, /* Virtual CPU interface */ +#endif { -1, 0 } }; static struct arm_gic_softc *arm_gic_sc = NULL; -#define gic_c_read_4(_sc, _reg) \ - bus_space_read_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg)) -#define gic_c_write_4(_sc, _reg, _val) \ - bus_space_write_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg), (_val)) -#define gic_d_read_4(_sc, _reg) \ - bus_space_read_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg)) -#define gic_d_write_4(_sc, _reg, _val) \ - bus_space_write_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg), (_val)) - static int gic_config_irq(int irq, enum intr_trigger trig, enum intr_polarity pol); static void gic_post_filter(void *); @@ -146,6 +83,12 @@ {NULL, false} }; +struct arm_gic_softc * +get_arm_gic_sc(void) +{ + return arm_gic_sc; +} + static int arm_gic_probe(device_t dev) { Added: soc2015/mihai/bhyve-on-arm-head/sys/arm/include/gic.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ soc2015/mihai/bhyve-on-arm-head/sys/arm/include/gic.h Mon Aug 10 18:38:00 2015 (r289530) @@ -0,0 +1,107 @@ +#ifndef _MACHINE_GIC_H_ +#define _MACHINE_GIC_H_ + +#include <machine/bus.h> + +/* We are using GICv2 register naming */ + +/* Distributor Registers */ +#define GICD_CTLR 0x000 /* v1 ICDDCR */ +#define GICD_TYPER 0x004 /* v1 ICDICTR */ +#define GICD_IIDR 0x008 /* v1 ICDIIDR */ +#define GICD_IGROUPR(n) (0x0080 + ((n) * 4)) /* v1 ICDISER */ +#define GICD_ISENABLER(n) (0x0100 + ((n) * 4)) /* v1 ICDISER */ +#define GICD_ICENABLER(n) (0x0180 + ((n) * 4)) /* v1 ICDICER */ +#define GICD_ISPENDR(n) (0x0200 + ((n) * 4)) /* v1 ICDISPR */ +#define GICD_ICPENDR(n) (0x0280 + ((n) * 4)) /* v1 ICDICPR */ +#define GICD_ICACTIVER(n) (0x0380 + ((n) * 4)) /* v1 ICDABR */ +#define GICD_IPRIORITYR(n) (0x0400 + ((n) * 4)) /* v1 ICDIPR */ +#define GICD_ITARGETSR(n) (0x0800 + ((n) * 4)) /* v1 ICDIPTR */ +#define GICD_ICFGR(n) (0x0C00 + ((n) * 4)) /* v1 ICDICFR */ +#define GICD_SGIR(n) (0x0F00 + ((n) * 4)) /* v1 ICDSGIR */ + +/* CPU Registers */ +#define GICC_CTLR 0x0000 /* v1 ICCICR */ +#define GICC_PMR 0x0004 /* v1 ICCPMR */ +#define GICC_BPR 0x0008 /* v1 ICCBPR */ +#define GICC_IAR 0x000C /* v1 ICCIAR */ +#define GICC_EOIR 0x0010 /* v1 ICCEOIR */ +#define GICC_RPR 0x0014 /* v1 ICCRPR */ +#define GICC_HPPIR 0x0018 /* v1 ICCHPIR */ +#define GICC_ABPR 0x001C /* v1 ICCABPR */ +#define GICC_IIDR 0x00FC /* v1 ICCIIDR*/ + +#define GIC_FIRST_IPI 0 /* Irqs 0-15 are SGIs/IPIs. */ +#define GIC_LAST_IPI 15 +#define GIC_FIRST_PPI 16 /* Irqs 16-31 are private (per */ +#define GIC_LAST_PPI 31 /* core) peripheral interrupts. */ +#define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */ + +/* First bit is a polarity bit (0 - low, 1 - high) */ +#define GICD_ICFGR_POL_LOW (0 << 0) +#define GICD_ICFGR_POL_HIGH (1 << 0) +#define GICD_ICFGR_POL_MASK 0x1 +/* Second bit is a trigger bit (0 - level, 1 - edge) */ +#define GICD_ICFGR_TRIG_LVL (0 << 1) +#define GICD_ICFGR_TRIG_EDGE (1 << 1) +#define GICD_ICFGR_TRIG_MASK 0x2 + + +#ifdef VMM_ARM_VGIC +#define GICH_HCR 0x0 +#define GICH_VTR 0x4 +#define GICH_VMCR 0x8 +#define GICH_MISR 0x10 +#define GICH_EISR0 0x20 +#define GICH_EISR1 0x24 +#define GICH_ELSR0 0x30 +#define GICH_ELSR1 0x34 +#define GICH_APR 0xF0 +#define GICH_LR0 0x100 +#endif + +#ifndef GIC_DEFAULT_ICFGR_INIT +#define GIC_DEFAULT_ICFGR_INIT 0x00000000 +#endif + +#ifdef VMM_ARM_VGIC +#define GIC_RES_COUNT 5 +#else +#define GIC_RES_COUNT 3 +#endif + +struct arm_gic_softc { + device_t gic_dev; + struct resource * gic_res[GIC_RES_COUNT]; + bus_space_tag_t gic_c_bst; + bus_space_tag_t gic_d_bst; + bus_space_handle_t gic_c_bsh; + bus_space_handle_t gic_d_bsh; +#ifdef VMM_ARM_VGIC + bus_space_tag_t gic_h_bst; + bus_space_handle_t gic_h_bsh; +#endif + uint8_t ver; + struct mtx mutex; + uint32_t nirqs; +}; + +#define gic_c_read_4(_sc, _reg) \ + bus_space_read_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg)) +#define gic_c_write_4(_sc, _reg, _val) \ + bus_space_write_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg), (_val)) +#define gic_d_read_4(_sc, _reg) \ + bus_space_read_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg)) +#define gic_d_write_4(_sc, _reg, _val) \ + bus_space_write_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg), (_val)) + +#ifdef VMM_ARM_VGIC +#define gic_h_read_4(_sc, _reg) \ + bus_space_read_4((_sc)->gic_h_bst, (_sc)->gic_h_bsh, (_reg)) +#define gic_h_write_4(_sc, _reg, _val) \ + bus_space_write_4((_sc)->gic_h_bst, (_sc)->gic_h_bsh, (_reg), (_val)) +#endif + +struct arm_gic_softc *get_arm_gic_sc(void); + +#endif
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