Date: Thu, 05 Aug 1999 19:05:48 +1000 From: Chris <reman@tig.com.au> To: John-Mark Gurney <gurney_j@resnet.uoregon.edu> Cc: Dag-Erling Smorgrav <des@flood.ping.uio.no>, freebsd-hackers@FreeBSD.ORG Subject: Re: Results of investigating optimizing calloc()... Message-ID: <37A953EC.AB5E9F90@tig.com.au> References: <001e01bedde3$d1af64c0$291c453f@kbyanc.alcnet.com> <xzpemhjpzac.fsf@flood.ping.uio.no> <19990804202932.50575@hydrogen.fircrest.net>
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John-Mark Gurney wrote: > > Dag-Erling Smorgrav scribbled this message on Aug 4: > > "Kelly Yancey" <kbyanc@alcnet.com> writes: > > > [...] > > > > Which reminds me - has anyone thought of using DMA for zeroing pages, > > to avoid cache invalidation? The idea is to keep a chunk of zeroes on > > disk and DMA it into memory instead of clearing pages "manually". This > > assumes your disk supports DMA, of course. > > has anyone looked at using two dma channels tied together to do memory > copies? I haven't studied the DMA specs, but from what I know of the > dma on x86 machines is that you could tie two dma channels together one > to feed the other, and this would allow you to copy memory w/o using the > processor... > > w/ dma channels, we can just make a copy of the base zero page... Im not sure how much relevance this has, but many years ago I was writing video routines, I thought using software initiated DMA to copy pages of memory from one place to another would be a really cool and quick solution. From what I remember you need to set the 0th DMA chanel with a src and dst address, then the number of bytes - set a flag and away she went. It was strange in that the DMA controller could only access the first 1Mb of memory and it couldnt cross 64kb page boundaries. Now AFAIK that has changed slightly and the DMA chip can do up to 128Kb page boundaries, however I'm not sure wether it can do 32bit addressing. However there was a drawback if the CPU had nothing else to do it could actually transfer memory around quicker than the DMA controller (The DMA controller on my PC was going at ISA bus speed ~8Mhz) Not sure what it does now, must go at at least 33Mhz for PCI DMA's. Also now that I remember it, the 0th DMA channel back then was also used a DRAM refresh timer going off every few milliseconds to keep the charges up on the DRAM's. Weird eh? Anyways thats all I can think of. The only way I can see that using DMA to refresh pages as a faster method is if the DMA controller can do it quicker than the CPU which I doubt is likely, also it will only be useful if it can do 32-bit addresses. sorry for the ramble. regards, chris -- Christopher Day E-Mail reman@tig.com.au Homepage http://www.geocities.com/TimesSquare/Lair/1218 when the rain/when the children reign/keep your conscience in the dark melt the statues in the park - Fall On Me, REM To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hackers" in the body of the message
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