Date: Sun, 13 Oct 2002 20:14:27 -0600 (MDT) From: "M. Warner Losh" <imp@bsdimp.com> To: dillon@apollo.backplane.com Cc: arch@FreeBSD.ORG Subject: Re: Database indexes and ram Message-ID: <20021013.201427.98861313.imp@bsdimp.com> In-Reply-To: <200210131900.g9DJ0ZAM054777@apollo.backplane.com> References: <3DA9B4A8.194A02FC@mindspring.com> <20021013.120847.31902907.imp@bsdimp.com> <200210131900.g9DJ0ZAM054777@apollo.backplane.com>
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In message: <200210131900.g9DJ0ZAM054777@apollo.backplane.com>
Matthew Dillon <dillon@apollo.backplane.com> writes:
: Google is your friend. I found a quick reference on the PCI bus.
: A 32 bit PCI bus can support 64 bit addresses through the use of
: two address cycles prefacing the data transfer.
Right, but the cards have to support it as well, and most of the pci
cards extant today simply do not support 64-bit operations. The
64-bit bit in BARS is set to 0 (well, more accuratelly, the decode
size field is set to 00 or 01, meaning 4G or 1M of decode logic
respectively). This means that most of them are incapible of
generating the 64-bit addresses needed to do dma above 4G. Maybe the
bridge chipsets support it, but very few cards do (and none of the
ones that I've brushed up against, but I tend to get cards at the low
end of the spectrum).
Warner
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