Date: Wed, 5 Dec 2012 21:27:05 GMT From: Robert Watson <rwatson@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 219888 for review Message-ID: <201212052127.qB5LR5nh086081@skunkworks.freebsd.org>
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http://p4web.freebsd.org/@@219888?ac=10 Change 219888 by rwatson@rwatson_zenith_cl_cam_ac_uk on 2012/12/05 21:26:57 Update CHERI assembly code for storing and loading data via capabilities, following an assembler update. Immediates are now supported. Affected files ... .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#15 edit Differences ... ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#15 (text+ko) ==== @@ -167,64 +167,62 @@ * XXXRW: immediates not yet supported by the assembler. */ #define CHERI_CSB(rs, rt, offset, cb) do { \ - __asm__ __volatile__ ("csb %0, %1($c%2)" : : \ - "r" (rs), "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("csb %0, %1, %2($c%3)" : : \ + "r" (rs), "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) #define CHERI_CSH(rs, rt, offset, cb) do { \ - __asm__ __volatile__ ("csh %0, %1($c%2)" : : \ - "r" (rs), "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("csh %0, %1, %2($c%3)" : : \ + "r" (rs), "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) #define CHERI_CSW(rs, rt, offset, cb) do { \ - __asm__ __volatile__ ("csw %0, %1($c%2)" : : \ - "r" (rs), "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("csw %0, %1, %2($c%3)" : : \ + "r" (rs), "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) #define CHERI_CSD(rs, rt, offset, cb) do { \ - __asm__ __volatile__ ("csd %0, %1($c%2)" : : \ - "r" (rs), "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("csd %0, %1, %2($c%3)" : : \ + "r" (rs), "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) /* * Data loads: while these don't much with c0, they do require memory * clobbers. - * - * XXXRW: immediates not yet supported by the assembler. */ #define CHERI_CLB(rd, rt, offset, cb) do { \ - __asm__ __volatile__ ("clb %0, %1($c%2)" : \ - "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("clb %0, %1, %2($c%3)" : \ + "=r" (rd) : "r" (rt), "i" (offset),"i" (cb) : "memory"); \ } while (0) #define CHERI_CLH(rd, rt, offset, cb) do { \ - __asm__ __volatile__ ("clh %0, %1($c%2)" : \ - "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("clh %0, %1, %2($c%3)" : \ + "=r" (rd) : "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) #define CHERI_CLW(rd, rt, offset, cb) do { \ - __asm__ __volatile__ ("clw %0, %1($c%2)" : \ - "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("clw %0, %1, %2($c%3)" : \ + "=r" (rd) : "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) #define CHERI_CLD(rd, rt, offset, cb) do { \ - __asm__ __volatile__ ("cld %0, %1($c%2)" : \ - "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("cld %0, %1, %2($c%3)" : \ + "=r" (rd) : "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) #define CHERI_CLBU(rd, rt, offset, cb) do { \ - __asm__ __volatile__ ("clbu %0, %1($c%2)" : \ - "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("clbu %0, %1, %2($c%3)" : \ + "=r" (rd) : "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) #define CHERI_CLHU(rd, rt, offset, cb) do { \ - __asm__ __volatile__ ("clhu %0, %1($c%2)" : \ - "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("clhu %0, %1, %2($c%3)" : \ + "=r" (rd) : "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) #define CHERI_CLWU(rd, rt, offset, cb) do { \ - __asm__ __volatile__ ("clwu %0, %1($c%2)" : \ - "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("clwu %0, %1, %2($c%3)" : \ + "=r" (rd) : "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) /*
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