Date: Tue, 17 Jul 2018 11:47:56 +0000 (UTC) From: Hans Petter Selasky <hselasky@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r336410 - head/sys/dev/mlx5/mlx5_core Message-ID: <201807171147.w6HBluFJ091552@repo.freebsd.org>
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Author: hselasky Date: Tue Jul 17 11:47:56 2018 New Revision: 336410 URL: https://svnweb.freebsd.org/changeset/base/336410 Log: Add module parameter to limit number of MSIX EQ vectors in mlx5en(4). For setups having a large amount of PCI devices, it makes sense to limit the number of MSIX vectors per PCI device, in order to avoid running out of IRQ vectors. MFC after: 1 week Sponsored by: Mellanox Technologies Modified: head/sys/dev/mlx5/mlx5_core/mlx5_main.c Modified: head/sys/dev/mlx5/mlx5_core/mlx5_main.c ============================================================================== --- head/sys/dev/mlx5/mlx5_core/mlx5_main.c Tue Jul 17 11:44:04 2018 (r336409) +++ head/sys/dev/mlx5/mlx5_core/mlx5_main.c Tue Jul 17 11:47:56 2018 (r336410) @@ -61,6 +61,10 @@ static int prof_sel = MLX5_DEFAULT_PROF; module_param_named(prof_sel, prof_sel, int, 0444); MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); +static int mlx5_core_msix_eqvec; +module_param_named(msix_eqvec, mlx5_core_msix_eqvec, int, 0644); +MODULE_PARM_DESC(msix_eqvec, "Maximum number of MSIX event queue vectors"); + #define NUMA_NO_NODE -1 static LIST_HEAD(intf_list); @@ -239,11 +243,15 @@ static int mlx5_enable_msix(struct mlx5_core_dev *dev) struct mlx5_priv *priv = &dev->priv; struct mlx5_eq_table *table = &priv->eq_table; int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); - int nvec; + int limit = mlx5_core_msix_eqvec; + int nvec = MLX5_EQ_VEC_COMP_BASE; int i; - nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() + - MLX5_EQ_VEC_COMP_BASE; + if (limit > 0) + nvec += limit; + else + nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus(); + nvec = min_t(int, nvec, num_eqs); if (nvec <= MLX5_EQ_VEC_COMP_BASE) return -ENOMEM;
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