Date: Sun, 22 Nov 2009 11:17:31 +0000 (UTC) From: Alexander Motin <mav@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r199645 - head/sys/dev/ata/chipsets Message-ID: <200911221117.nAMBHVcB016590@svn.freebsd.org>
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Author: mav Date: Sun Nov 22 11:17:31 2009 New Revision: 199645 URL: http://svn.freebsd.org/changeset/base/199645 Log: Fix Intel PATA UDMA timings setting, affecting write performance. Binary divider value 10 specified in datasheet is not a hex 0x10. UDMA2 should be 33/2 instead of 66/4, which is documented as reverved, UDMA4 should be 66/2 instead of 66/4, which is definitely wrong. Modified: head/sys/dev/ata/chipsets/ata-intel.c Modified: head/sys/dev/ata/chipsets/ata-intel.c ============================================================================== --- head/sys/dev/ata/chipsets/ata-intel.c Sun Nov 22 10:53:26 2009 (r199644) +++ head/sys/dev/ata/chipsets/ata-intel.c Sun Nov 22 11:17:31 2009 (r199645) @@ -319,7 +319,7 @@ ata_intel_new_setmode(device_t dev, int ata_mode2str(mode), ctlr->chip->text); if (!error) { if (mode >= ATA_UDMA0) { - u_int8_t utimings[] = { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 }; + u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2); pci_write_config(gparent, 0x4a, @@ -331,7 +331,7 @@ ata_intel_new_setmode(device_t dev, int pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); } reg54 |= 0x0400; - if (mode >= ATA_UDMA2) + if (mode >= ATA_UDMA3) reg54 |= (0x1 << devno); else reg54 &= ~(0x1 << devno);
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