Date: Mon, 18 Aug 2014 13:13:20 -0700 From: Peter Grehan <grehan@freebsd.org> To: alc@freebsd.org, Konstantin Belousov <kostikbel@gmail.com> Cc: arch@freebsd.org, Gleb Smirnoff <glebius@freebsd.org>, "Alexander V. Chernikov" <melifaro@freebsd.org>, "Andrey V. Elsukov" <ae@freebsd.org> Subject: Re: superpages for UMA Message-ID: <53F25E60.5050109@freebsd.org> In-Reply-To: <CAJUyCcM7ZipmYu8OLxT2TCPjS%2BCSTGPRnotdKgchoNQH8s8ndA@mail.gmail.com> References: <53F215A9.8010708@FreeBSD.org> <20140818183925.GP2737@kib.kiev.ua> <CAJUyCcM7ZipmYu8OLxT2TCPjS%2BCSTGPRnotdKgchoNQH8s8ndA@mail.gmail.com>
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> Newer Intel CPUs have more entries, and AMD CPUs have long (since > Barcelona) had more. In particular, they allow 2 MB page mappings to be > cached in a larger L2 TLB. Nowadays, the trouble is with the 1 GB pages. > A lot of CPUs still only support an 8 entry, 1 level TLB for 1 GB pages. There are new(ish) ones effectively without 1GB pages. From the "Software Optimization Guide for AMD Family 16h Processors" "Smashing" ... "when the Family 16h processor encounters a 1-Gbyte page size, it will smash translations of that 1-Gbyte region into 2-Mbyte TLB entries, each of which translates a 2-Mbyte region of the 1-Gbyte page." later, Peter.
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