Date: Thu, 29 Jul 2010 18:14:32 GMT From: Hans Petter Selasky <hselasky@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 181571 for review Message-ID: <201007291814.o6TIEWLV011026@repoman.freebsd.org>
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http://p4web.freebsd.org/@@181571?ac=10 Change 181571 by hselasky@hselasky_laptop001 on 2010/07/29 18:13:36 USB controller: - add more XHCI header file definitions Affected files ... .. //depot/projects/usb/src/sys/dev/usb/controller/xhci.h#3 edit Differences ... ==== //depot/projects/usb/src/sys/dev/usb/controller/xhci.h#3 (text+ko) ==== @@ -28,6 +28,9 @@ #define XHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) #define XHCI_MAX_ENDPOINTS 32 +#define XHCI_MAX_SCRATCHPADS 32 +#define XHCI_MAX_EVENTS (16 * 7) +#define XHCI_MAX_COMMANDS (16 * 7) #define XHCI_DEV_CTX_ADDR_ALIGN 64 /* bytes */ #define XHCI_DEV_CTX_ALIGN 64 /* bytes */ @@ -38,7 +41,6 @@ #define XHCI_TRANS_RING_SEG_ALIGN 16 /* bytes */ #define XHCI_CMD_RING_SEG_ALIGN 64 /* bytes */ #define XHCI_EVENT_RING_SEG_ALIGN 64 /* bytes */ -#define XHCI_EVENT_RING_SEG_TAB_ALIGN 64 /* bytes */ #define XHCI_SCRATCH_BUF_ARRAY_ALIGN 64 /* bytes */ #define XHCI_SCRATCH_BUFFER_ALIGN USB_PAGE_SIZE #define XHCI_TRB_ALIGN 16 /* bytes */ @@ -47,7 +49,7 @@ volatile uint64_t qwBaaDevCtxAddr; volatile uint64_t qwBaaScratchAddr; #define XHCI_BAA_MASK 0xFFFFFFFFFFFFFFE0ULL -} __aligned(XHCI_DEV_CTX_ADDR_ALIGN); +}; struct xhci_slot_ctx { volatile uint32_t dwSctx0; @@ -86,7 +88,7 @@ volatile uint32_t dwSctx5; volatile uint32_t dwSctx6; volatile uint32_t dwSctx7; -} __aligned(XHCI_SLOT_CTX_ALIGN); +}; struct xhci_endp_ctx { volatile uint32_t dwEpCtx0; @@ -123,7 +125,7 @@ volatile uint32_t dwEpCtx5; volatile uint32_t dwEpCtx6; volatile uint32_t dwEpCtx7; -} __aligned(XHCI_ENDP_CTX_ALIGN); +}; struct xhci_input_ctx { volatile uint32_t dwInCtx0; @@ -136,13 +138,14 @@ volatile uint32_t dwInCtx5; volatile uint32_t dwInCtx6; volatile uint32_t dwInCtx7; -} __aligned(XHCI_INPUT_CTX_ALIGN); +}; struct xhci_dev_ctx { - struct xhci_slot_ctx ctx_input; - struct xhci_slot_ctx ctx_slot; - struct xhci_endp_ctx ctx_ep0; - struct xhci_endp_ctx ctx_epN[XHCI_MAX_ENDPOINTS - 2]; + struct xhci_slot_ctx ctx_input; + struct xhci_slot_ctx ctx_slot; + struct xhci_endp_ctx ctx_ep0; + struct xhci_endp_ctx ctx_epN[XHCI_MAX_ENDPOINTS - 2]; + volatile uint64_t ctx_sp_buf_ptr[XHCI_MAX_SCRATCHPADS]; } __aligned(XHCI_DEV_CTX_ALIGN); struct xhci_stream_ctx { @@ -162,12 +165,210 @@ #define XHCI_SCTX_0_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U volatile uint32_t dwSctx2; volatile uint32_t dwSctx3; -} __aligned(XHCI_STREAM_CTX_ALIGN); +}; struct xhci_trb { volatile uint64_t qwTrb0; volatile uint32_t dwTrb2; +#define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF) +#define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24) +#define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F) +#define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17) +#define XHCI_TRB_2_BYTES_GET(x) ((x) & 0xFFFF) +#define XHCI_TRB_2_BYTES_SET(x) ((x) & 0xFFFF) +#define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF) +#define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22) + volatile uint32_t dwTrb3; +#define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F) +#define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10) +#define XHCI_TRB_3_CYCLE_BIT (1U << 0) +#define XHCI_TRB_3_ENT_BIT (1U << 1) +#define XHCI_TRB_3_ISP_BIT (1U << 2) +#define XHCI_TRB_3_NSNOOP_BIT (1U << 3) +#define XHCI_TRB_3_CHAIN_BIT (1U << 4) +#define XHCI_TRB_3_IOC_BIT (1U << 5) +#define XHCI_TRB_3_IDT_BIT (1U << 6) +#define XHCI_TRB_3_BEI_BIT (1U << 9) +#define XHCI_TRB_3_TRT_MASK (3U << 16) +#define XHCI_TRB_3_TRT_NONE (0U << 16) +#define XHCI_TRB_3_TRT_OUT (2U << 16) +#define XHCI_TRB_3_TRT_IN (3U << 16) +#define XHCI_TRB_3_DIR_IN (1U << 16) +#define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF) +#define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16) +#define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF) +#define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20) +#define XHCI_TRB_3_ISO_SIA_BIT (1U << 31) + +/* Commands */ +#define XHCI_TRB_TYPE_RESERVED 0x00 +#define XHCI_TRB_TYPE_NORMAL 0x01 +#define XHCI_TRB_TYPE_SETUP_STAGE 0x02 +#define XHCI_TRB_TYPE_DATA_STAGE 0x03 +#define XHCI_TRB_TYPE_STATUS_STAGE 0x04 +#define XHCI_TRB_TYPE_ISOCH 0x05 +#define XHCI_TRB_TYPE_LINK 0x06 +#define XHCI_TRB_TYPE_EVENT_DATA 0x07 +#define XHCI_TRB_TYPE_NOOP 0x08 +#define XHCI_TRB_TYPE_ENABLE_SLOT 0x09 +#define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A +#define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B +#define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C +#define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D +#define XHCI_TRB_TYPE_RESET_EP 0x0E +#define XHCI_TRB_TYPE_STOP_EP 0x0F +#define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10 +#define XHCI_TRB_TYPE_RESET_DEVICE 0x11 +#define XHCI_TRB_TYPE_FORCE_EVENT 0x12 +#define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13 +#define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14 +#define XHCI_TRB_TYPE_GET_PORT_BW 0x15 +#define XHCI_TRB_TYPE_FORCE_HEADER 0x16 +#define XHCI_TRB_TYPE_NOOP_CMD 0x17 + +/* Events */ +#define XHCI_TRB_EVENT_TRANSFER 0x20 +#define XHCI_TRB_EVENT_CMD_COMPLETE 0x21 +#define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22 +#define XHCI_TRB_EVENT_BW_REQUEST 0x23 +#define XHCI_TRB_EVENT_DOORBELL 0x24 +#define XHCI_TRB_EVENT_HOST_CTRL 0x25 +#define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26 +#define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27 + +/* Error codes */ +#define XHCI_TRB_ERROR_INVALID 0x00 +#define XHCI_TRB_ERROR_SUCCESS 0x01 +#define XHCI_TRB_ERROR_DATA_BUF 0x02 +#define XHCI_TRB_ERROR_BABBLE 0x03 +#define XHCI_TRB_ERROR_XACT 0x04 +#define XHCI_TRB_ERROR_TRB 0x05 +#define XHCI_TRB_ERROR_STALL 0x06 +#define XHCI_TRB_ERROR_RESOURCE 0x07 +#define XHCI_TRB_ERROR_BANDWIDTH 0x08 +#define XHCI_TRB_ERROR_NO_SLOTS 0x09 +#define XHCI_TRB_ERROR_STREAM_TYPE 0x0A +#define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B +#define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C +#define XHCI_TRB_ERROR_SHORT_PKT 0x0D +#define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E +#define XHCI_TRB_ERROR_RING_OVERRUN 0x0F +#define XHCI_TRB_ERROR_VF_RING_FULL 0x10 +#define XHCI_TRB_ERROR_PARAMETER 0x11 +#define XHCI_TRB_ERROR_BW_OVERRUN 0x12 +#define XHCI_TRB_ERROR_CONTEXT_STATE 0x13 +#define XHCI_TRB_ERROR_NO_PING_RESP 0x14 +#define XHCI_TRB_ERROR_EV_RING_FULL 0x15 +#define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16 +#define XHCI_TRB_ERROR_MISSED_SERVICE 0x17 +#define XHCI_TRB_ERROR_CMD_RING_STOP 0x18 +#define XHCI_TRB_ERROR_CMD_ABORTED 0x19 +#define XHCI_TRB_ERROR_STOPPED 0x1A +#define XHCI_TRB_ERROR_LENGTH 0x1B +#define XHCI_TRB_ERROR_BAD_MELAT 0x1D +#define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F +#define XHCI_TRB_ERROR_EVENT_LOST 0x20 +#define XHCI_TRB_ERROR_UNDEFINED 0x21 +#define XHCI_TRB_ERROR_INVALID_SID 0x22 +#define XHCI_TRB_ERROR_SEC_BW 0x23 +#define XHCI_TRB_ERROR_SPLIT_XACT 0x24 +}; + +#define XHCI_TD_PAGE_NBUF 5 /* units */ +#define XHCI_TD_PAGE_SIZE 4096 /* bytes */ +#define XHCI_TD_PAYLOAD_MAX (XHCI_TD_PAGE_SIZE * (XHCI_TD_PAGE_NBUF - 1)) + +struct xhci_td { + struct xhci_trb td_trb[XHCI_TD_PAGE_NBUF + 1]; + +/* + * Extra information needed: + */ + uint64_t td_self; + struct xhci_td *next; + struct xhci_td *alt_next; + struct xhci_td *obj_next; + struct usb_page_cache *page_cache; + uint16_t len; + uint8_t ntrb; + } __aligned(XHCI_TRB_ALIGN); +struct xhci_event_ring_seg { + volatile uint64_t qwEvrsTablePtr; + volatile uint32_t dwEvrsTableSize; + volatile uint32_t dwEvrsReserved; +}; + +struct xhci_hw_root { + struct xhci_event_ring_seg hwr_ring_seg[4]; + struct xhci_trb hwr_events[XHCI_MAX_EVENTS]; + struct xhci_trb hwr_commands[XHCI_MAX_COMMANDS]; +}; + +struct xhci_hw_softc { + struct usb_page_cache root_pc; + struct usb_page_cache device_pc[XHCI_MAX_DEVICES]; + struct usb_page_cache device_input_pc[XHCI_MAX_DEVICES]; + struct usb_page_cache device_sp_pc[XHCI_MAX_DEVICES][XHCI_MAX_SCRATCHPAD]; + + struct usb_page root_pg; + struct usb_page device_pg[XHCI_MAX_DEVICES]; + struct usb_page device_input_pg[XHCI_MAX_DEVICES]; + struct usb_page device_sp_pg[XHCI_MAX_DEVICES][XHCI_MAX_SCRATCHPAD]; +}; + +struct xhci_config_desc { + struct usb_config_descriptor confd; + struct usb_interface_descriptor ifcd; + struct usb_endpoint_descriptor endpd; + struct usb_endpoint_ss_comp_descriptor endpcd; +} __packed; + +union xhci_hub_desc { + struct usb_status stat; + struct usb_port_status ps; + struct usb_hub_ss_descriptor hubd; + uint8_t temp[128]; +}; + +struct xhci_softc { + struct xhci_hw_softc sc_hw; + struct usb_bus sc_bus; /* base device */ + + union xhci_hub_desc sc_hub_desc; + + struct usb_device *sc_devices[XHCI_MAX_DEVICES]; + struct resource *sc_io_res; + struct resource *sc_irq_res; + + void *sc_intr_hdl; + bus_size_t sc_io_size; + bus_space_tag_t sc_io_tag; + bus_space_handle_t sc_io_hdl; + + uint32_t sc_eintrs; + uint32_t sc_cmd; /* shadow of cmd register during + * suspend */ + + uint16_t sc_flags; /* chip specific flags */ + + uint16_t sc_pcib_off; /* offset to PCI registers */ + uint16_t sc_oper_off; /* offset to operational registers */ + uint16_t sc_capa_off; /* offset to capability registers */ + uint16_t sc_port_off; /* offset to port status registers */ + uint16_t sc_runt_off; /* offset to runtime registers */ + uint16_t sc_door_off; /* offset to doorbell registers */ + + uint8_t sc_noport; /* number of ports on root HUB */ + uint8_t sc_addr; /* root HUB device address */ + uint8_t sc_conf; /* root HUB device configuration */ + uint8_t sc_isreset; + uint8_t sc_hub_idata[2]; + + char sc_vendor[16]; /* vendor string for root hub */ + +}; + #endif /* _XHCI_H_ */
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