Date: Wed, 17 Mar 2010 15:36:53 +0100 From: Rafal Jaworowski <raj@semihalf.com> To: Grzegorz Bernacki <gjb@semihalf.com> Cc: embedded@freebsd.org, Andrew Turner <andrew@fubar.geek.nz>, Luiz Otavio O Souza <loos.br@gmail.com> Subject: Re: NAND Flash Framework for review Message-ID: <1F3290BD-674B-4ED6-98DB-FCFE8B2DF4F4@semihalf.com> In-Reply-To: <4B9F72BC.1050609@semihalf.com> References: <0AE04EFA-A3EB-4939-BD81-607C00355B67@semihalf.com> <20100314165825.121d346b@fubar.geek.nz> <CC419602-A9E8-4FE2-A5A5-0BFBD8240EDD@gmail.com> <4B9E1697.9090602@semihalf.com> <20100316101044.0401295e@fubar.geek.nz> <4B9F72BC.1050609@semihalf.com>
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On 2010-03-16, at 12:59, Grzegorz Bernacki wrote: > Andrew Turner wrote: >> On Mon, 15 Mar 2010 12:14:31 +0100 >> Grzegorz Bernacki <gjb@semihalf.com> wrote: >>>>> Chip drivers: >>>>> - lnand and snand have magic numbers to figure out which drive to >>>>> use. We should move these to a flag in the chip parameters. >>>> We just need to add the chip size in nand_params and based on that >>>> we can calculate the number of address cycles (see below) and the >>>> type of chip (if chip >=3D 128MB and pagesize > 512 then you have a >>>> large page device). >>>>=20 >>> Yes, I was thinking about adding size of page and column address to >>> parameters of nfc_send_address. >> Why not just send each address byte separately like when the command = is >> sent? This will then push the requirement to know how many address >> bytes to the chip driver. >=20 > I choose to send whole address in one call to make implementation of = mpc8572 > driver easier. This controller requires to divide address into block = number and > page & column number and write them into corresponding registers. It = would be > complicated (however, not impossible) to combine full address from = bytes sending > via consecutive nfc_send_address calls. On the other hand sending = whole address > in one call should not complicated drivers for controllers which just = send address > byte after byte. For Andrewa nad Luiz reference I have submitted the existing MPC85XX = NAND back-end driver to the P4 branch. Rafal
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