Date: Wed, 10 Aug 2016 12:41:36 +0000 (UTC) From: Ruslan Bukin <br@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r303908 - in head/sys: boot/fdt/dts/riscv conf riscv/conf riscv/htif riscv/include riscv/riscv Message-ID: <201608101241.u7ACfaZ9050891@repo.freebsd.org>
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Author: br Date: Wed Aug 10 12:41:36 2016 New Revision: 303908 URL: https://svnweb.freebsd.org/changeset/base/303908 Log: o Remove operation in machine mode. Machine privilege level was specially designed to use in vendor's firmware or bootloader. We have implemented operation in machine mode in FreeBSD as part of understanding RISC-V ISA, but it is time to remove it. We now use BBL (Berkeley Boot Loader) -- standard RISC-V firmware, which provides operation in machine mode for us. We now use standard SBI calls to machine mode, instead of handmade 'syscalls'. o Remove HTIF bus. HTIF bus is now legacy and no longer exists in RISC-V specification. HTIF code still exists in Spike simulator, but BBL do not provide raw interface to it. Memory disk is only choice for now to have multiuser booted in Spike, until Spike has implemented more devices (e.g. Virtio, etc). Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Added: head/sys/riscv/include/sbi.h (contents, props changed) head/sys/riscv/riscv/riscv_console.c (contents, props changed) head/sys/riscv/riscv/sbi.S (contents, props changed) Deleted: head/sys/riscv/htif/ Modified: head/sys/boot/fdt/dts/riscv/qemu.dts head/sys/boot/fdt/dts/riscv/rocket.dts head/sys/boot/fdt/dts/riscv/spike.dts head/sys/conf/files.riscv head/sys/conf/ldscript.riscv head/sys/riscv/conf/GENERIC head/sys/riscv/conf/QEMU head/sys/riscv/conf/ROCKET head/sys/riscv/conf/SPIKE head/sys/riscv/include/cpufunc.h head/sys/riscv/include/pcpu.h head/sys/riscv/include/riscvreg.h head/sys/riscv/include/vmparam.h head/sys/riscv/riscv/exception.S head/sys/riscv/riscv/genassym.c head/sys/riscv/riscv/identcpu.c head/sys/riscv/riscv/intr_machdep.c head/sys/riscv/riscv/locore.S head/sys/riscv/riscv/machdep.c head/sys/riscv/riscv/mp_machdep.c head/sys/riscv/riscv/pmap.c head/sys/riscv/riscv/timer.c head/sys/riscv/riscv/vm_machdep.c Modified: head/sys/boot/fdt/dts/riscv/qemu.dts ============================================================================== --- head/sys/boot/fdt/dts/riscv/qemu.dts Wed Aug 10 12:36:54 2016 (r303907) +++ head/sys/boot/fdt/dts/riscv/qemu.dts Wed Aug 10 12:41:36 2016 (r303908) @@ -72,15 +72,11 @@ clock-frequency = < 400000000 >; }; - htif0: htif@0 { - compatible = "riscv,htif"; - interrupts = < 0 >; + console0: console@0 { + compatible = "riscv,console"; + status = "okay"; + interrupts = < 1 >; interrupt-parent = < &pic0 >; - - console0: console@0 { - compatible = "htif,console"; - status = "okay"; - }; }; }; Modified: head/sys/boot/fdt/dts/riscv/rocket.dts ============================================================================== --- head/sys/boot/fdt/dts/riscv/rocket.dts Wed Aug 10 12:36:54 2016 (r303907) +++ head/sys/boot/fdt/dts/riscv/rocket.dts Wed Aug 10 12:41:36 2016 (r303908) @@ -83,15 +83,11 @@ clock-frequency = < 1000000 >; }; - htif0: htif@0 { - compatible = "riscv,htif"; - interrupts = < 0 >; + console0: console@0 { + compatible = "riscv,console"; + status = "okay"; + interrupts = < 1 >; interrupt-parent = < &pic0 >; - - console0: console@0 { - compatible = "htif,console"; - status = "okay"; - }; }; }; Modified: head/sys/boot/fdt/dts/riscv/spike.dts ============================================================================== --- head/sys/boot/fdt/dts/riscv/spike.dts Wed Aug 10 12:36:54 2016 (r303907) +++ head/sys/boot/fdt/dts/riscv/spike.dts Wed Aug 10 12:41:36 2016 (r303908) @@ -65,6 +65,10 @@ }; memory { + /* + * This is not used currently. + * We take information from sbi_query_memory. + */ device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1GB at 0x80000000 */ }; @@ -90,15 +94,11 @@ clock-frequency = < 1000000 >; }; - htif0: htif@0 { - compatible = "riscv,htif"; + console0: console@0 { + compatible = "riscv,console"; + status = "okay"; interrupts = < 1 >; interrupt-parent = < &pic0 >; - - console0: console@0 { - compatible = "htif,console"; - status = "okay"; - }; }; }; Modified: head/sys/conf/files.riscv ============================================================================== --- head/sys/conf/files.riscv Wed Aug 10 12:36:54 2016 (r303907) +++ head/sys/conf/files.riscv Wed Aug 10 12:41:36 2016 (r303908) @@ -19,9 +19,6 @@ libkern/flsl.c standard libkern/flsll.c standard libkern/memmove.c standard libkern/memset.c standard -riscv/htif/htif.c optional htif -riscv/htif/htif_block.c optional htif -riscv/htif/htif_console.c optional htif riscv/riscv/autoconf.c standard riscv/riscv/bcopy.c standard riscv/riscv/bus_machdep.c standard @@ -36,6 +33,7 @@ riscv/riscv/db_interface.c optional ddb riscv/riscv/db_trace.c optional ddb riscv/riscv/dump_machdep.c standard riscv/riscv/elf_machdep.c standard +riscv/riscv/exception.S standard riscv/riscv/intr_machdep.c standard riscv/riscv/in_cksum.c optional inet | inet6 riscv/riscv/identcpu.c standard @@ -47,6 +45,8 @@ riscv/riscv/mem.c standard riscv/riscv/nexus.c standard riscv/riscv/ofw_machdep.c optional fdt riscv/riscv/pmap.c standard +riscv/riscv/riscv_console.c optional rcons +riscv/riscv/sbi.S standard riscv/riscv/stack_machdep.c optional ddb | stack riscv/riscv/support.S standard riscv/riscv/swtch.S standard Modified: head/sys/conf/ldscript.riscv ============================================================================== --- head/sys/conf/ldscript.riscv Wed Aug 10 12:36:54 2016 (r303907) +++ head/sys/conf/ldscript.riscv Wed Aug 10 12:41:36 2016 (r303908) @@ -6,7 +6,7 @@ SEARCH_DIR(/usr/lib); SECTIONS { /* Read-only sections, merged into text segment: */ - . = kernbase + 0x80000000 /* KERNENTRY */; + . = kernbase; .text : AT(ADDR(.text) - kernbase) { *(.text) Modified: head/sys/riscv/conf/GENERIC ============================================================================== --- head/sys/riscv/conf/GENERIC Wed Aug 10 12:36:54 2016 (r303907) +++ head/sys/riscv/conf/GENERIC Wed Aug 10 12:41:36 2016 (r303908) @@ -76,7 +76,7 @@ options SMP # Uncomment for memory disk # options MD_ROOT -# options MD_ROOT_SIZE=8192 # 8MB ram disk +# options MD_ROOT_SIZE=32768 # 32MB ram disk # makeoptions MFS_IMAGE=/path/to/img # options ROOTDEVNAME=\"ufs:/dev/md0\" Modified: head/sys/riscv/conf/QEMU ============================================================================== --- head/sys/riscv/conf/QEMU Wed Aug 10 12:36:54 2016 (r303907) +++ head/sys/riscv/conf/QEMU Wed Aug 10 12:41:36 2016 (r303908) @@ -21,8 +21,8 @@ include GENERIC ident QEMU -device htif -options ROOTDEVNAME=\"ufs:/dev/htif_blk0\" +device rcons +options ROOTDEVNAME=\"ufs:/dev/md0\" # RISCVTODO: This needs to be done via loader (when it's available). options FDT_DTB_STATIC Modified: head/sys/riscv/conf/ROCKET ============================================================================== --- head/sys/riscv/conf/ROCKET Wed Aug 10 12:36:54 2016 (r303907) +++ head/sys/riscv/conf/ROCKET Wed Aug 10 12:41:36 2016 (r303908) @@ -21,8 +21,8 @@ include GENERIC ident ROCKET -device htif -options ROOTDEVNAME=\"ufs:/dev/htif_blk0\" +device rcons +options ROOTDEVNAME=\"ufs:/dev/md0\" # RISCVTODO: This needs to be done via loader (when it's available). options FDT_DTB_STATIC Modified: head/sys/riscv/conf/SPIKE ============================================================================== --- head/sys/riscv/conf/SPIKE Wed Aug 10 12:36:54 2016 (r303907) +++ head/sys/riscv/conf/SPIKE Wed Aug 10 12:41:36 2016 (r303908) @@ -21,8 +21,8 @@ include GENERIC ident SPIKE -device htif -options ROOTDEVNAME=\"ufs:/dev/htif_blk0\" +device rcons +options ROOTDEVNAME=\"ufs:/dev/md0\" # RISCVTODO: This needs to be done via loader (when it's available). options FDT_DTB_STATIC Modified: head/sys/riscv/include/cpufunc.h ============================================================================== --- head/sys/riscv/include/cpufunc.h Wed Aug 10 12:36:54 2016 (r303907) +++ head/sys/riscv/include/cpufunc.h Wed Aug 10 12:41:36 2016 (r303908) @@ -81,21 +81,6 @@ intr_enable(void) ); } -static __inline register_t -machine_command(uint64_t cmd, uint64_t arg) -{ - uint64_t res; - - __asm __volatile( - "mv t5, %2\n" - "mv t6, %1\n" - "ecall\n" - "mv %0, t6" : "=&r"(res) : "r"(arg), "r"(cmd) - ); - - return (res); -} - #define cpu_nullop() riscv_nullop() #define cpufunc_nullop() riscv_nullop() #define cpu_setttb(a) riscv_setttb(a) Modified: head/sys/riscv/include/pcpu.h ============================================================================== --- head/sys/riscv/include/pcpu.h Wed Aug 10 12:36:54 2016 (r303907) +++ head/sys/riscv/include/pcpu.h Wed Aug 10 12:41:36 2016 (r303908) @@ -46,8 +46,7 @@ #define PCPU_MD_FIELDS \ uint32_t pc_pending_ipis; /* IPIs pending to this CPU */ \ - uint64_t pc_reg; /* CPU MMIO base (PA) */ \ - char __pad[117] + char __pad[125] #ifdef _KERNEL Modified: head/sys/riscv/include/riscvreg.h ============================================================================== --- head/sys/riscv/include/riscvreg.h Wed Aug 10 12:36:54 2016 (r303907) +++ head/sys/riscv/include/riscvreg.h Wed Aug 10 12:41:36 2016 (r303908) @@ -37,19 +37,6 @@ #ifndef _MACHINE_RISCVREG_H_ #define _MACHINE_RISCVREG_H_ -/* Machine mode requests */ -#define ECALL_MTIMECMP 0x01 -#define ECALL_HTIF_GET_ENTRY 0x02 -#define ECALL_MCPUID_GET 0x03 -#define ECALL_MIMPID_GET 0x04 -#define ECALL_SEND_IPI 0x05 -#define ECALL_CLEAR_IPI 0x06 -#define ECALL_MIE_SET 0x07 -#define ECALL_IO_IRQ_MASK 0x08 -#define ECALL_HTIF_CMD 0x09 -#define ECALL_HTIF_CMD_REQ 0x0a -#define ECALL_HTIF_CMD_RESP 0x0b - #define EXCP_SHIFT 0 #define EXCP_MASK (0xf << EXCP_SHIFT) #define EXCP_MISALIGNED_FETCH 0 @@ -65,9 +52,6 @@ #define EXCP_HYPERVISOR_ECALL 10 #define EXCP_MACHINE_ECALL 11 #define EXCP_INTR (1ul << 63) -#define EXCP_INTR_SOFTWARE 0 -#define EXCP_INTR_TIMER 1 -#define EXCP_INTR_HTIF 2 #define SSTATUS_UIE (1 << 0) #define SSTATUS_SIE (1 << 1) Added: head/sys/riscv/include/sbi.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/riscv/include/sbi.h Wed Aug 10 12:41:36 2016 (r303908) @@ -0,0 +1,65 @@ +/*- + * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com> + * All rights reserved. + * + * Portions of this software were developed by SRI International and the + * University of Cambridge Computer Laboratory under DARPA/AFRL contract + * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Portions of this software were developed by the University of Cambridge + * Computer Laboratory as part of the CTSRD Project, with support from the + * UK Higher Education Innovation Fund (HEIF). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_SBI_H_ +#define _MACHINE_SBI_H_ + +typedef struct { + uint64_t base; + uint64_t size; + uint64_t node_id; +} memory_block_info; + +uint64_t sbi_query_memory(uint64_t id, memory_block_info *p); +uint64_t sbi_hart_id(void); +uint64_t sbi_num_harts(void); +uint64_t sbi_timebase(void); +void sbi_set_timer(uint64_t stime_value); +void sbi_send_ipi(uint64_t hart_id); +uint64_t sbi_clear_ipi(void); +void sbi_shutdown(void); + +void sbi_console_putchar(unsigned char ch); +int sbi_console_getchar(void); + +void sbi_remote_sfence_vm(uint64_t hart_mask_ptr, uint64_t asid); +void sbi_remote_sfence_vm_range(uint64_t hart_mask_ptr, uint64_t asid, uint64_t start, uint64_t size); +void sbi_remote_fence_i(uint64_t hart_mask_ptr); + +uint64_t sbi_mask_interrupt(uint64_t which); +uint64_t sbi_unmask_interrupt(uint64_t which); + +#endif /* !_MACHINE_SBI_H_ */ Modified: head/sys/riscv/include/vmparam.h ============================================================================== --- head/sys/riscv/include/vmparam.h Wed Aug 10 12:36:54 2016 (r303907) +++ head/sys/riscv/include/vmparam.h Wed Aug 10 12:41:36 2016 (r303908) @@ -156,26 +156,26 @@ #define VM_MIN_KERNEL_ADDRESS (0xffffffc000000000UL) #define VM_MAX_KERNEL_ADDRESS (0xffffffc800000000UL) -/* Direct Map for 128 GiB of PA: 0x0 - 0x1fffffffff */ +/* 128 GiB maximum for the direct map region */ #define DMAP_MIN_ADDRESS (0xffffffd000000000UL) -#define DMAP_MAX_ADDRESS (0xffffffefffffffffUL) +#define DMAP_MAX_ADDRESS (0xfffffff000000000UL) -#define DMAP_MIN_PHYSADDR (0x0000000000000000UL) -#define DMAP_MAX_PHYSADDR (DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) +#define DMAP_MIN_PHYSADDR (dmap_phys_base) +#define DMAP_MAX_PHYSADDR (dmap_phys_max) /* True if pa is in the dmap range */ #define PHYS_IN_DMAP(pa) ((pa) >= DMAP_MIN_PHYSADDR && \ - (pa) <= DMAP_MAX_PHYSADDR) + (pa) < DMAP_MAX_PHYSADDR) /* True if va is in the dmap range */ #define VIRT_IN_DMAP(va) ((va) >= DMAP_MIN_ADDRESS && \ - (va) <= DMAP_MAX_ADDRESS) + (va) < (dmap_max_addr)) #define PHYS_TO_DMAP(pa) \ ({ \ KASSERT(PHYS_IN_DMAP(pa), \ ("%s: PA out of range, PA: 0x%lx", __func__, \ (vm_paddr_t)(pa))); \ - (pa) | DMAP_MIN_ADDRESS; \ + ((pa) - dmap_phys_base) + DMAP_MIN_ADDRESS; \ }) #define DMAP_TO_PHYS(va) \ @@ -183,7 +183,7 @@ KASSERT(VIRT_IN_DMAP(va), \ ("%s: VA out of range, VA: 0x%lx", __func__, \ (vm_offset_t)(va))); \ - (va) & ~DMAP_MIN_ADDRESS; \ + ((va) - DMAP_MIN_ADDRESS) + dmap_phys_base; \ }) #define VM_MIN_USER_ADDRESS (0x0000000000000000UL) @@ -196,7 +196,7 @@ #define SHAREDPAGE (VM_MAXUSER_ADDRESS - PAGE_SIZE) #define USRSTACK SHAREDPAGE -#define KERNENTRY (0x80000000) +#define KERNENTRY (0) /* * How many physical pages per kmem arena virtual page. @@ -233,9 +233,14 @@ * #define UMA_MD_SMALL_ALLOC */ +#ifndef LOCORE +extern vm_paddr_t dmap_phys_base; +extern vm_paddr_t dmap_phys_max; +extern vm_offset_t dmap_max_addr; extern u_int tsb_kernel_ldd_phys; extern vm_offset_t vm_max_kernel_address; extern vm_offset_t init_pt_va; +#endif #define ZERO_REGION_SIZE (64 * 1024) /* 64KB */ Modified: head/sys/riscv/riscv/exception.S ============================================================================== --- head/sys/riscv/riscv/exception.S Wed Aug 10 12:36:54 2016 (r303907) +++ head/sys/riscv/riscv/exception.S Wed Aug 10 12:41:36 2016 (r303908) @@ -235,388 +235,3 @@ ENTRY(cpu_exception_handler_user) csrrw sp, sscratch, sp sret END(cpu_exception_handler_user) - -/* - * Trap handlers - */ - .text -bad_trap: - j bad_trap - -machine_trap: - /* Save state */ - csrrw sp, mscratch, sp - addi sp, sp, -64 - sd t0, (8 * 0)(sp) - sd t1, (8 * 1)(sp) - sd t2, (8 * 2)(sp) - sd t3, (8 * 3)(sp) - sd t4, (8 * 4)(sp) - sd t5, (8 * 5)(sp) - sd a0, (8 * 7)(sp) - - csrr t3, mstatus /* Required for debug */ - csrr t0, mcause - bltz t0, machine_interrupt - - li t1, EXCP_SUPERVISOR_ECALL - beq t0, t1, supervisor_call -4: - /* NOT REACHED */ - j 4b - -machine_interrupt: - /* Type of interrupt ? */ - csrr t0, mcause - andi t0, t0, EXCP_MASK -#if 0 - /* lowRISC TODO */ - li t1, 4 - beq t1, t0, io_interrupt /* lowRISC only */ -#endif - li t1, 1 - beq t1, t0, supervisor_software_interrupt - li t1, 3 - beq t1, t0, machine_software_interrupt - li t1, 5 - beq t1, t0, supervisor_timer_interrupt - li t1, 7 - beq t1, t0, machine_timer_interrupt - - /* NOT REACHED */ -1: - j 1b - -#if 0 - /* lowRISC TODO */ -io_interrupt: - /* Disable IO interrupts so we can go to supervisor mode */ - csrwi CSR_IO_IRQ, 0 - - /* Handle the trap in supervisor mode */ - j exit_mrts -#endif - -supervisor_software_interrupt: -1: - /* Nothing here as we are using mideleg feature */ - j 1b - -machine_software_interrupt: - /* Clear IPI */ - li t0, 0x40001000 - csrr t2, mhartid - li t3, 0x1000 - mul t2, t2, t3 - add t0, t0, t2 - li t2, 0 - sd t2, 0(t0) - - /* Clear machine software pending bit */ - li t0, MIP_MSIP - csrc mip, t0 - - /* Post supervisor software interrupt */ - li t0, MIP_SSIP - csrs mip, t0 - - j exit - -supervisor_timer_interrupt: -1: - /* Nothing here as we are using mideleg feature */ - j 1b - -machine_timer_interrupt: - /* Disable machine timer interrupts */ - li t0, MIE_MTIE - csrc mie, t0 - - /* Clear machine timer interrupt pending */ - li t0, MIP_MTIP - csrc mip, t0 - - /* Post supervisor timer interrupt */ - li t0, MIP_STIP - csrs mip, t0 - - /* - * Check for HTIF interrupts. - * The only interrupt expected here is key press. - */ - la t0, htif_lock - li t2, 1 - amoswap.d t3, t2, 0(t0) - bnez t3, 5f /* Another operation in progress, give up */ - - /* We have lock */ - la t1, fromhost - ld t5, 0(t1) - beqz t5, 4f - - /* Console GET intr ? */ - mv t1, t5 - li t0, 0x100 - srli t1, t1, 48 - beq t1, t0, 2f -1: - /* There is no interrupts except keypress */ - j 1b - -2: - /* Save entry */ - la t0, htif_ring - li t4, (HTIF_RING_SIZE) - add t0, t0, t4 /* t0 == htif_ring_cursor */ - - ld t1, 0(t0) /* load ptr to cursor */ - sd t5, 0(t1) /* put entry */ - li t4, 1 - sd t4, 8(t1) /* mark used */ - ld t4, 16(t1) /* take next */ - /* Update cursor */ - sd t4, 0(t0) - - /* Post supervisor software interrupt */ - li t0, MIP_SSIP - csrs mip, t0 - -3: - la t1, fromhost - li t5, 0 - sd t5, 0(t1) - -4: - /* Release lock */ - la t0, htif_lock - li t2, 0 - amoswap.d t3, t2, 0(t0) - -5: - j exit - -supervisor_call: - csrr t1, mepc - addi t1, t1, 4 /* Next instruction in t1 */ - li t4, ECALL_HTIF_CMD - beq t5, t4, htif_cmd - li t4, ECALL_HTIF_CMD_REQ - beq t5, t4, htif_cmd_req - li t4, ECALL_HTIF_CMD_RESP - beq t5, t4, htif_cmd_resp - li t4, ECALL_HTIF_GET_ENTRY - beq t5, t4, htif_get_entry - li t4, ECALL_MTIMECMP - beq t5, t4, set_mtimecmp - li t4, ECALL_MCPUID_GET - beq t5, t4, mcpuid_get - li t4, ECALL_MIMPID_GET - beq t5, t4, mimpid_get - li t4, ECALL_SEND_IPI - beq t5, t4, send_ipi - li t4, ECALL_CLEAR_IPI - beq t5, t4, clear_ipi - li t4, ECALL_MIE_SET - beq t5, t4, mie_set -#if 0 - /* lowRISC TODO */ - li t4, ECALL_IO_IRQ_MASK - beq t5, t4, io_irq_mask -#endif - j exit_next_instr - -#if 0 - /* lowRISC TODO */ -io_irq_mask: - csrw CSR_IO_IRQ, t6 - j exit_next_instr -#endif - -mie_set: - csrs mie, t6 - j exit_next_instr - -mcpuid_get: - csrr t6, misa - j exit_next_instr - -mimpid_get: - csrr t6, mimpid - j exit_next_instr - -send_ipi: - /* CPU ipi MMIO register in t6 */ - mv t0, t6 - li t2, 1 - sd t2, 0(t0) - j exit_next_instr - -clear_ipi: - /* Do only clear if there are no new entries in HTIF ring */ - la t0, htif_ring - li t4, (HTIF_RING_SIZE) - add t0, t0, t4 /* t0 == ptr to htif_ring_cursor */ - ld t2, 8(t0) /* load htif_ring_last */ - ld t2, 8(t2) /* load used */ - bnez t2, 1f - - /* Clear supervisor software interrupt pending bit */ - li t0, MIP_SSIP - csrc mip, t0 - -1: - j exit_next_instr - -htif_get_entry: - /* Get a htif_ring for current core */ - la t0, htif_ring - li t4, (HTIF_RING_SIZE + 8) - add t0, t0, t4 /* t0 == htif_ring_last */ - - /* Check for new entries */ - li t6, 0 /* preset return value */ - ld t2, 0(t0) /* load ptr to last */ - ld t4, 8(t2) /* get used */ - beqz t4, 1f /* No new entries. Exit */ - - /* Get one */ - ld t6, 0(t2) /* get entry */ - li t4, 0 - sd t4, 8(t2) /* mark free */ - sd t4, 0(t2) /* free entry, just in case */ - ld t4, 16(t2) /* take next */ - sd t4, 0(t0) /* update ptr to last */ -1: - /* Exit. Result is stored in t6 */ - j exit_next_instr - -htif_cmd_resp: - la t0, htif_lock - li t2, 1 -1: - amoswap.d t3, t2, 0(t0) - bnez t3, 1b - - /* We have lock. Read for data */ - la t4, fromhost - ld t6, 0(t4) - beqz t6, 2f - - /* Clear event */ - li t5, 0 - sd t5, 0(t4) - -2: - /* Release lock */ - la t0, htif_lock - li t2, 0 - amoswap.d t3, t2, 0(t0) - - j exit_next_instr - -htif_cmd_req: - la t0, htif_lock - li t2, 1 -1: - amoswap.d t3, t2, 0(t0) - bnez t3, 1b - - /* We have lock. Store new request */ - la t4, tohost - sd t6, 0(t4) - - /* Release lock */ - la t0, htif_lock - li t2, 0 - amoswap.d t3, t2, 0(t0) - - j exit_next_instr - -htif_cmd: - la t0, htif_lock - li t2, 1 -1: - amoswap.d t3, t2, 0(t0) - bnez t3, 1b - - mv t3, t6 - - /* We have lock. Store new request */ - la t4, tohost - sd t6, 0(t4) -2: - /* Poll for result */ - la t4, fromhost - ld t6, 0(t4) - beqz t6, 2b - - /* Check for unexpected event */ - srli t0, t6, 48 - srli t2, t3, 48 - beq t2, t0, 3f - - /* - * We have something unexpected (e.g. keyboard keypress) - * Save entry. - */ - la t0, htif_ring - li t4, (HTIF_RING_SIZE) - add t0, t0, t4 /* t0 == htif_ring_cursor */ - - ld t2, 0(t0) /* load ptr to cursor */ - sd t6, 0(t2) /* put entry */ - li t4, 1 - sd t4, 8(t2) /* mark used */ - ld t4, 16(t2) /* take next */ - /* Update cursor */ - sd t4, 0(t0) - - /* Post supervisor software interrupt */ - li t0, MIP_SSIP - csrs mip, t0 - - /* Clear and look for response again */ - la t2, fromhost - li t5, 0 - sd t5, 0(t2) - j 2b - -3: - la t2, fromhost - li t5, 0 - sd t5, 0(t2) - - /* Release lock */ - la t0, htif_lock - li t2, 0 - amoswap.d t3, t2, 0(t0) - - j exit_next_instr - -set_mtimecmp: - /* Enable interrupts */ - li t0, (MIE_MTIE | MIE_STIE) - csrs mie, t0 - j exit_next_instr - -/* - * Trap exit functions - */ -exit_next_instr: - /* Next instruction is in t1 */ - csrw mepc, t1 -exit: - /* Restore state */ - ld t0, (8 * 0)(sp) - ld t1, (8 * 1)(sp) - ld t2, (8 * 2)(sp) - ld t3, (8 * 3)(sp) - ld t4, (8 * 4)(sp) - ld t5, (8 * 5)(sp) - ld a0, (8 * 7)(sp) - addi sp, sp, 64 - csrrw sp, mscratch, sp - mret - -exit_mrts: - j exit_mrts Modified: head/sys/riscv/riscv/genassym.c ============================================================================== --- head/sys/riscv/riscv/genassym.c Wed Aug 10 12:36:54 2016 (r303907) +++ head/sys/riscv/riscv/genassym.c Wed Aug 10 12:41:36 2016 (r303908) @@ -57,7 +57,6 @@ __FBSDID("$FreeBSD$"); #include <machine/intr.h> ASSYM(KERNBASE, KERNBASE); -ASSYM(KERNENTRY, KERNENTRY); ASSYM(VM_MAXUSER_ADDRESS, VM_MAXUSER_ADDRESS); ASSYM(VM_MAX_KERNEL_ADDRESS, VM_MAX_KERNEL_ADDRESS); ASSYM(TDF_ASTPENDING, TDF_ASTPENDING); Modified: head/sys/riscv/riscv/identcpu.c ============================================================================== --- head/sys/riscv/riscv/identcpu.c Wed Aug 10 12:36:54 2016 (r303907) +++ head/sys/riscv/riscv/identcpu.c Wed Aug 10 12:41:36 2016 (r303908) @@ -101,8 +101,9 @@ identify_cpu(void) cpu_partsp = NULL; - mimpid = machine_command(ECALL_MIMPID_GET, 0); - misa = machine_command(ECALL_MCPUID_GET, 0); + /* TODO: can we get mimpid and misa somewhere ? */ + mimpid = 0; + misa = 0; cpu = PCPU_GET(cpuid); Modified: head/sys/riscv/riscv/intr_machdep.c ============================================================================== --- head/sys/riscv/riscv/intr_machdep.c Wed Aug 10 12:36:54 2016 (r303907) +++ head/sys/riscv/riscv/intr_machdep.c Wed Aug 10 12:41:36 2016 (r303908) @@ -47,6 +47,7 @@ __FBSDID("$FreeBSD$"); #include <machine/cpufunc.h> #include <machine/frame.h> #include <machine/intr.h> +#include <machine/sbi.h> #ifdef SMP #include <machine/smp.h> @@ -267,7 +268,7 @@ ipi_send(struct pcpu *pc, int ipi) CTR3(KTR_SMP, "%s: cpu=%d, ipi=%x", __func__, pc->pc_cpuid, ipi); atomic_set_32(&pc->pc_pending_ipis, ipi); - machine_command(ECALL_SEND_IPI, pc->pc_reg); + sbi_send_ipi(pc->pc_cpuid); CTR1(KTR_SMP, "%s: sent", __func__); } Modified: head/sys/riscv/riscv/locore.S ============================================================================== --- head/sys/riscv/riscv/locore.S Wed Aug 10 12:36:54 2016 (r303907) +++ head/sys/riscv/riscv/locore.S Wed Aug 10 12:41:36 2016 (r303908) @@ -43,118 +43,47 @@ #include <machine/riscvreg.h> #include <machine/pte.h> -#define HTIF_RING_NENTRIES (512) -#define HTIF_RING_ENTRY_SZ (24) -#define HTIF_RING_SIZE (HTIF_RING_ENTRY_SZ * HTIF_RING_NENTRIES) -#define HW_STACK_SIZE (96) - -/* - * Event queue: - * - * struct htif_ring { - * uint64_t data; - * uint64_t used; - * uint64_t next; - * } htif_ring[HTIF_RING_NENTRIES]; - * uint64_t htif_ring_cursor; - * uint64_t htif_ring_last; - */ - -.macro build_ring - la t0, htif_ring - li t1, 0 - sd t1, 0(t0) /* zero data */ - sd t1, 8(t0) /* zero used */ - mv t2, t0 - mv t3, t0 - li t5, (HTIF_RING_SIZE) - li t6, 0 - add t4, t0, t5 -1: - addi t3, t3, HTIF_RING_ENTRY_SZ /* pointer to next */ - beq t3, t4, 2f /* finish */ - sd t3, 16(t2) /* store pointer */ - addi t2, t2, HTIF_RING_ENTRY_SZ /* next entry */ - addi t6, t6, 1 /* counter */ - j 1b -2: - addi t3, t3, -HTIF_RING_ENTRY_SZ - sd t0, 16(t3) /* last -> first */ - - li t2, (HTIF_RING_SIZE) - add s0, t0, t2 - sd t0, 0(s0) /* cursor */ - sd t0, 8(s0) /* last */ - /* finish building ring */ -.endm - .globl kernbase .set kernbase, KERNBASE /* Trap entries */ .text -mentry: - /* Vectors */ - j _start /* reset */ - j bad_trap /* NMI (non-maskable interrupt) */ - j machine_trap - /* Reset vector */ .text .globl _start _start: - /* Setup machine trap vector */ - la t0, machine_trap - csrw mtvec, t0 - - /* Delegate interrupts to supervisor mode */ - li t0, (MIP_SSIP | MIP_STIP | MIP_SEIP) - csrw mideleg, t0 - - /* Delegate exceptions to supervisor mode */ - li t0, (1 << EXCP_MISALIGNED_FETCH) | \ - (1 << EXCP_FAULT_FETCH) | \ - (1 << EXCP_ILLEGAL_INSTRUCTION) | \ - (1 << EXCP_FAULT_LOAD) | \ - (1 << EXCP_FAULT_STORE) | \ - (1 << EXCP_BREAKPOINT) | \ - (1 << EXCP_USER_ECALL) - csrw medeleg, t0 - + /* Setup supervisor trap vector */ la t0, cpu_exception_handler - li t1, KERNBASE - add t0, t0, t1 csrw stvec, t0 - /* Direct secondary cores to mpentry */ - csrr a0, mhartid - bnez a0, mpentry - - li t1, 0 - la t0, tohost - sd t1, 0(t0) - la t0, fromhost - sd t1, 0(t0) - - /* Build event queue for current core */ - build_ring - - /* Setup machine-mode stack for CPU 0 */ - la t0, hardstack_end - csrw mscratch, t0 - + /* Ensure sscratch is zero */ li t0, 0 csrw sscratch, t0 - li s10, PAGE_SIZE - li s9, (PAGE_SIZE * KSTACK_PAGES) + /* Load physical memory information */ + li a0, 0 + la a1, memory_info + call sbi_query_memory + + /* Store base to s6 */ + la s6, memory_info + ld s6, 0(s6) /* s6 = physmem base */ - /* Page tables */ + /* Direct secondary cores to mpentry */ + call sbi_hart_id + bnez a0, mpentry + + /* + * Page tables + */ /* Create an L1 page for early devmap */ la s1, pagetable_l1 la s2, pagetable_l2_devmap /* Link to next level PN */ + li t0, KERNBASE + sub s2, s2, t0 + add s2, s2, s6 srli s2, s2, PAGE_SHIFT li a5, (VM_MAX_KERNEL_ADDRESS - L2_SIZE) @@ -170,19 +99,74 @@ _start: add t0, s1, a5 sd t6, (t0) - /* Add single Level 1 entry for kernel */ + /* Create an L1 page for SBI */ + la s1, pagetable_l1 + la s2, pagetable_l2_sbi /* Link to next level PN */ + li t0, KERNBASE + sub s2, s2, t0 + add s2, s2, s6 + srli s2, s2, PAGE_SHIFT + li a5, 511 + li t4, PTE_V + slli t5, s2, PTE_PPN0_S /* (s2 << PTE_PPN0_S) */ + or t6, t4, t5 + + /* Store SBI L1 PTE entry to position */ + li a6, PTE_SIZE + mulw a5, a5, a6 + add t0, s1, a5 + sd t6, (t0) + + /* Create an L2 page for SBI */ + la s1, pagetable_l2_sbi + la s2, pagetable_l3_sbi /* Link to next level PN */ + li t0, KERNBASE + sub s2, s2, t0 + add s2, s2, s6 + srli s2, s2, PAGE_SHIFT + li a5, 511 + li t4, PTE_V + slli t5, s2, PTE_PPN0_S /* (s2 << PTE_PPN0_S) */ + or t6, t4, t5 + + /* Store SBI L2 PTE entry to position */ + li a6, PTE_SIZE + mulw a5, a5, a6 + add t0, s1, a5 + sd t6, (t0) + + /* Create an L3 page for SBI */ + la s1, pagetable_l3_sbi + li s2, 0x80009000 + srli s2, s2, PAGE_SHIFT + li a5, 511 + li t4, PTE_V | PTE_RX | PTE_W + slli t5, s2, PTE_PPN0_S /* (s2 << PTE_PPN0_S) */ + or t6, t4, t5 + + /* Store SBI L3 PTE entry to position */ + li a6, PTE_SIZE + mulw a5, a5, a6 + add t0, s1, a5 *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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