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Date:      Mon, 2 Mar 2015 02:24:46 +0000 (UTC)
From:      Adrian Chadd <adrian@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r279513 - head/sys/mips/conf
Message-ID:  <201503020224.t222OkwP028356@svn.freebsd.org>

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Author: adrian
Date: Mon Mar  2 02:24:46 2015
New Revision: 279513
URL: https://svnweb.freebsd.org/changeset/base/279513

Log:
  Bring over the initial QCA955x SoC support framework.
  
  This is enough to bring up the basic SoC support.
  
  What works thus far:
  
  * The mips74k core, pll setup, and UART (or else well, stuff would
    be really difficult..)
  * both USB 2.0 EHCI controllers
  * on-board 2GHz 3x3 wifi (the other variant has 2GHz/5GHz wifi on-chip);
  * arge0 - not yet sure why arge1 isn't firing off interrupts and thus
    handling traffic, but I will soon figure it out and fix it here.
  
  Tested:
  
  * AP135 reference design, QCA9558 SoC, pretending to be an 11n
    2GHz AP.
  
  TODO:
  
  * There's an interrupt mux hooking up devices to IP2 and IP3 - but it's
    not a read-and-clear or write-to-clear register.  So, trying to use it
    naively like I have been ends up with massive interrupt storms.
    For now the things that share those interrupts can just take them as
    shared interrupts and try to play nice.
  
  * There's two PCIe root complexes /and/ one of them can actually be
    a PCIe device endpoint.  Yes, you heard right.  I have to teach the
    AR724x PCIe bridge code to handle multiple instances with multiple
    memory/irq regions, and then there'll be RC support, but EP support
    isn't on my TODO list.
  
  * I'm not sure why arge1 isn't up and running.  I'll go figure that
    out soon and fix it here.
  
  Thankyou to Qualcomm Atheros for providing me with hardware and
  an abundance of documentation about these things.

Added:
  head/sys/mips/conf/QCA955X_BASE   (contents, props changed)
  head/sys/mips/conf/QCA955X_BASE.hints   (contents, props changed)

Added: head/sys/mips/conf/QCA955X_BASE
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ head/sys/mips/conf/QCA955X_BASE	Mon Mar  2 02:24:46 2015	(r279513)
@@ -0,0 +1,147 @@
+#
+# QCA955X_BASE -- Kernel configuration base file for the Qualcomm Atheros
+# QCA955x SoC.
+#
+# This file (and the hints file accompanying it) are not designed to be
+# used by themselves. Instead, users of this file should create a kernel
+# config file which includes this file (which gets the basic hints), then
+# override the default options (adding devices as needed) and adding
+# hints as needed (for example, the GPIO and LAN PHY.)
+#
+# $FreeBSD$
+#
+
+machine         mips mips
+ident		QCA955X_BASE
+cpu		CPU_MIPS74KC
+makeoptions	KERNLOADADDR=0x80050000
+options 	HZ=1000
+
+options		BREAK_TO_DEBUGGER
+options		ALT_BREAK_TO_DEBUGGER
+
+# options		BOOTVERBOSE=10
+
+files		"../atheros/files.ar71xx"
+hints		"QCA955X_BASE.hints"
+
+makeoptions	DEBUG=-g		#Build kernel with gdb(1) debug symbols
+# makeoptions	MODULES_OVERRIDE="random gpio ar71xx if_gif if_gre if_bridge bridgestp usb wlan wlan_xauth wlan_acl wlan_wep wlan_tkip wlan_ccmp wlan_rssadapt wlan_amrr ath ath_ahb hwpmc"
+makeoptions	MODULES_OVERRIDE=""
+
+options 	DDB
+options 	KDB
+options 	ALQ
+
+options 	SCHED_4BSD		#4BSD scheduler
+options 	INET			#InterNETworking
+#options 	INET6			#InterNETworking
+#options 	NFSCL			#Network Filesystem Client
+options 	PSEUDOFS		#Pseudo-filesystem framework
+options 	_KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+
+# Don't include the SCSI/CAM strings in the default build
+options 	SCSI_NO_SENSE_STRINGS
+options 	SCSI_NO_OP_STRINGS
+
+# .. And no sysctl strings
+options 	NO_SYSCTL_DESCR
+
+# Limit IO size
+options 	NBUF=128
+
+# Limit UMTX hash size
+# options 	UMTX_NUM_CHAINS=64
+
+# PMC
+#options 	HWPMC_HOOKS
+#device		hwpmc
+#device		hwpmc_mips24k
+
+# options 	NFS_LEGACYRPC
+# Debugging for use in -current
+#options 	INVARIANTS
+#options 	INVARIANT_SUPPORT
+#options 	WITNESS
+#options 	WITNESS_SKIPSPIN
+options 	FFS                     #Berkeley Fast Filesystem
+#options 	SOFTUPDATES             #Enable FFS soft updates support
+#options 	UFS_ACL                 #Support for access control lists
+#options 	UFS_DIRHASH             #Improve performance on big directories
+options 	NO_FFS_SNAPSHOT		# We don't require snapshot support
+
+# Wireless NIC cards
+options 	IEEE80211_DEBUG
+options 	IEEE80211_SUPPORT_MESH
+options 	IEEE80211_SUPPORT_TDMA
+options 	IEEE80211_SUPPORT_SUPERG
+options 	IEEE80211_ALQ	# 802.11 ALQ logging support
+device		wlan            # 802.11 support
+device		wlan_wep        # 802.11 WEP support
+device		wlan_ccmp       # 802.11 CCMP support
+device		wlan_tkip       # 802.11 TKIP support
+device		wlan_xauth	# 802.11 hostap support
+
+# ath(4)
+device		ath             # Atheros network device
+device		ath_rate_sample
+device		ath_ahb		# Atheros host bus glue
+options 	ATH_DEBUG
+options 	ATH_DIAGAPI
+option		ATH_ENABLE_11N
+option 		AH_DEBUG_ALQ
+
+#device		ath_hal
+device		ath_ar9300		# AR9330 HAL; no need for the others
+option		AH_DEBUG
+option		AH_SUPPORT_AR5416	# 11n HAL support
+option		AH_SUPPORT_QCA9550	# Chipset support
+option		AH_DEBUG_ALQ
+option		AH_AR5416_INTERRUPT_MITIGATION
+
+device		mii
+device		arge
+options		ARGE_DEBUG
+
+device		usb
+options 	USB_EHCI_BIG_ENDIAN_DESC        # handle big-endian byte order
+options 	USB_DEBUG
+options 	USB_HOST_ALIGN=32		# AR71XX (MIPS in general?) requires this
+device		ehci
+
+device		pci
+# XXX TODO: need to write a qca955x_pci bridge
+# .. since it now handles >1 PCIe bus and the reset
+# registers may have changed a bit.
+# device		ar724x_pci
+
+device		scbus
+device		umass
+device		da
+
+device		spibus
+device		ar71xx_spi
+device		mx25l
+device		ar71xx_wdog
+
+device		uart
+device		uart_ar71xx
+
+device		ar71xx_apb
+# Until some better interrupt handling is shoehorned into qca955x_apb,
+# we'll have to stick to shared interrupts for IP2/IP3 demux.
+# device		qca955x_apb
+
+device		loop
+device		ether
+device		md
+device		bpf
+device		random
+device		if_bridge
+device		gpio
+device		gpioled
+
+#options		KTR
+#options		KTR_MASK=(KTR_INTR)
+#options		KTR_COMPILE=(KTR_INTR)
+#options		KTR_VERBOSE

Added: head/sys/mips/conf/QCA955X_BASE.hints
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ head/sys/mips/conf/QCA955X_BASE.hints	Mon Mar  2 02:24:46 2015	(r279513)
@@ -0,0 +1,79 @@
+# This file (and the kernel config file accompanying it) are not designed
+# to be used by themselves. Instead, users of this file should create a
+# kernel config file which includes this file (which gets the basic hints),
+# then override the default options (adding devices as needed) and adding
+# hints as needed (for example, the GPIO and LAN PHY.)
+
+# $FreeBSD$
+
+hint.apb.0.at="nexus0"
+# The default APB is on IP6 (irq4); we need to add
+# the two new ones (IP2, IP3) to this and extend
+# the irq ranges appropriately.
+hint.apb.0.irq=4
+
+# uart0
+hint.uart.0.at="apb0"
+# NB: This isn't an ns8250 UART
+hint.uart.0.maddr=0x18020003
+hint.uart.0.msize=0x18
+hint.uart.0.irq=3
+
+# ehci - on IP3
+hint.ehci.0.at="nexus0"
+hint.ehci.0.maddr=0x1b000100
+hint.ehci.0.msize=0x00001000
+hint.ehci.0.irq=1
+
+hint.ehci.1.at="nexus0"
+hint.ehci.1.maddr=0x1b400100
+hint.ehci.1.msize=0x00001000
+hint.ehci.1.irq=1
+
+# PCIe 1: qca955x_int0 (IP2)
+
+# pci - XXX no maddr/msize, grr!
+hint.pcib.0.at="nexus0"
+hint.pcib.0.irq=0
+
+# XXX TODO: PCIe 1: qca955x_int1 (IP3)
+
+# IP4
+hint.arge.0.at="nexus0"
+hint.arge.0.maddr=0x19000000
+hint.arge.0.msize=0x1000
+hint.arge.0.irq=2
+
+# IP5
+hint.arge.1.at="nexus0"
+hint.arge.1.maddr=0x1a000000
+hint.arge.1.msize=0x1000
+hint.arge.1.irq=3
+
+# ath0 - connected via IP2 mux
+hint.ath.0.at="nexus0"
+hint.ath.0.maddr=0x18100000
+hint.ath.0.msize=0x20000
+hint.ath.0.irq=0
+hint.ath.0.vendor_id=0x168c
+hint.ath.0.device_id=0x0039
+# Set this to define where the ath calibration data
+# should be fetched from in physical memory.
+# hint.ath.0.eepromaddr=0x1fff1000
+
+# SPI flash
+hint.spi.0.at="nexus0"
+hint.spi.0.maddr=0x1f000000
+hint.spi.0.msize=0x10
+
+hint.mx25l.0.at="spibus0"
+hint.mx25l.0.cs=0
+
+# Watchdog
+hint.ar71xx_wdog.0.at="nexus0"
+
+# The GPIO function and pin mask is configured per-board
+hint.gpio.0.at="apb0"
+hint.gpio.0.maddr=0x18040000
+hint.gpio.0.msize=0x1000
+hint.gpio.0.irq=2



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