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Date:      Fri, 3 Jul 2015 06:09:57 +0000 (UTC)
From:      Adrian Chadd <adrian@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r285079 - head/sys/mips/conf
Message-ID:  <201507030609.t6369viV086562@repo.freebsd.org>

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Author: adrian
Date: Fri Jul  3 06:09:56 2015
New Revision: 285079
URL: https://svnweb.freebsd.org/changeset/base/285079

Log:
  Add initial support for the TP-Link Archer C7 v2.
  
  The SoC, the flash, the ethernet ports and ethernet switch all work.
  The USB works.
  
  The 11ac PCIe NIC internally is at least seen by the PCIE RC, but
  I haven't tried using it yet.  There's no driver and I haven't
  yet swapped it out for a non-11ac chip.
  
  The on-chip 2GHz wifi works, but there are some data errors that
  get thrown up in STA mode when scanning.  I have a feeling I have
  to finish the DDR flush code out and have it run correctly on the
  shared interrupts; that'll take a bit of time to get right.
  
  But if you're after an updated piece of hardware, the Archer C7 v2
  is certainly there, and you can replace the 11ac NIC with a 3x3
  Atheros PCIe device (eg AR9380, AR9390, AR9580, etc) and it'll
  "just work".
  
  Tested:
  
  * TP-Link archer c7v2.

Added:
  head/sys/mips/conf/TL-ARCHERC7V2   (contents, props changed)
  head/sys/mips/conf/TL-ARCHERC7V2.hints   (contents, props changed)

Added: head/sys/mips/conf/TL-ARCHERC7V2
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ head/sys/mips/conf/TL-ARCHERC7V2	Fri Jul  3 06:09:56 2015	(r285079)
@@ -0,0 +1,68 @@
+#
+# TP-Link Archer C7 - based on the AP135 reference design.
+#
+# This contains a QCA9558 MIPS74k SoC with on-board 3x3 2GHz wifi,
+# 128MiB RAM, an AR8327 5-port gigabit ethernet switch and
+# a QCA 11ac 5GHz AP NIC.
+#
+# The to things not currently support are the QCA 11ac NIC and
+# PCIe host controllers - there's two of them, and the existing
+# PCIe code here doesn't support that just yet.
+#
+# $FreeBSD$
+#
+
+# Include the default QCA955x parameters
+include         "QCA955X_BASE"
+
+ident           TL-ARCHERC7V2
+
+# Override hints with board values
+hints           "TL-ARCHERC7V2.hints"
+
+# Force the board memory - this has 128MiB RAM
+options         AR71XX_REALMEM=(128*1024*1024)
+
+# i2c GPIO bus
+#device		gpioiic
+#device		iicbb
+#device		iicbus
+#device		iic
+
+# Options required for miiproxy and mdiobus
+options 	ARGE_MDIO	# Export an MDIO bus separate from arge
+device		miiproxy	# MDIO bus <-> MII PHY rendezvous
+
+device		etherswitch
+device		arswitch
+
+# read MSDOS formatted disks - USB
+options 	MSDOSFS
+
+# Enable the uboot environment stuff rather then the
+# redboot stuff.
+options 	AR71XX_ENV_UBOOT
+
+# uzip - to boot natively from flash
+device		geom_uncompress
+options 	GEOM_UNCOMPRESS
+
+# Used for the static uboot partition map
+device          geom_map
+
+# yes, this board has a PCIe connected atheros device
+# add ath_pci so it can at least attach things when there's a
+# ath(4) in there, rather than the 11ac chip we don't support.
+device		pci
+device		qca955x_pci
+
+device		ath_pci
+options 	AR71XX_ATH_EEPROM
+device		firmware		# Used by the above
+options 	ATH_EEPROM_FIRMWARE
+
+# Boot off of the rootfs, as defined in the geom_map setup.
+options 	ROOTDEVNAME=\"ufs:map/rootfs.uncompress\"
+
+# Default to accept
+options		IPFIREWALL_DEFAULT_TO_ACCEPT

Added: head/sys/mips/conf/TL-ARCHERC7V2.hints
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ head/sys/mips/conf/TL-ARCHERC7V2.hints	Fri Jul  3 06:09:56 2015	(r285079)
@@ -0,0 +1,201 @@
+# The Archer C7 v2 is based on the AP135-020 board, with
+# TP-Link specific bits (eg flash layout, MAC address, etc.)
+
+# $FreeBSD$
+
+# QCA955X_ETH_CFG_RGMII_EN (1 << 0)
+hint.qca955x_gmac.0.gmac_cfg=0x1
+
+# Use base mac address for wifi; +1 and +2 for arge0/arge1.
+hint.ar71xx.0.eeprom_mac_addr=0x1f01fc00
+hint.ar71xx.0.eeprom_mac_isascii=0
+
+hint.ar71xx_mac_map.0.devid=ath
+hint.ar71xx_mac_map.0.unitid=0
+hint.ar71xx_mac_map.0.offset=0
+hint.ar71xx_mac_map.0.is_local=0
+
+hint.ar71xx_mac_map.1.devid=arge
+hint.ar71xx_mac_map.1.unitid=0
+hint.ar71xx_mac_map.1.offset=1
+hint.ar71xx_mac_map.1.is_local=0
+
+hint.ar71xx_mac_map.2.devid=arge
+hint.ar71xx_mac_map.2.unitid=1
+hint.ar71xx_mac_map.2.offset=2
+hint.ar71xx_mac_map.2.is_local=0
+
+# mdiobus0 on arge0
+hint.argemdio.0.at="nexus0"
+hint.argemdio.0.maddr=0x19000000
+hint.argemdio.0.msize=0x1000
+hint.argemdio.0.order=0
+
+# mdiobus1 on arge1 - required to bring up arge1?
+hint.argemdio.1.at="nexus0"
+hint.argemdio.1.maddr=0x1a000000
+hint.argemdio.1.msize=0x1000
+hint.argemdio.1.order=0
+
+# AR8327 - connected via mdiobus0 on arge0
+hint.arswitch.0.at="mdio0"
+hint.arswitch.0.is_7240=0	# definitely not the internal switch!
+hint.arswitch.0.is_9340=0	# not the internal switch!
+hint.arswitch.0.numphys=5	# all ports are PHYs
+hint.arswitch.0.phy4cpu=0
+hint.arswitch.0.is_rgmii=0	# not needed
+hint.arswitch.0.is_gmii=0	# not needed
+
+# This is where it gets a bit odd. port 0 and port 6 are CPU ports.
+# The current code only supports one CPU port.  So hm, what should
+# we do to hook PAD6 up to be RGMII but a PHY, not a MAC?
+
+# The other trick - how do we get arge1 (hooked up to GMAC0) to work?
+# That's currently supposed to be hooked up to CPU port 0.
+
+# Other AR8327 configuration parameters
+
+# AP136-020 parameters
+
+# GMAC0 AR8327 -> GMAC1 (arge1) SoC, SGMII
+
+# AR8327_PAD_MAC_SGMII
+hint.arswitch.0.pad.0.mode=3
+#hint.arswitch.0.pad.0.rxclk_delay_sel=0
+hint.arswitch.0.pad.0.sgmii_delay_en=1
+
+# GMAC6 AR8327 -> GMAC0 (arge0) SoC, RGMII
+
+# AR8327_PAD_MAC_RGMII
+# XXX I think this hooks it up to the internal MAC6
+hint.arswitch.0.pad.6.mode=6
+hint.arswitch.0.pad.6.txclk_delay_en=1
+hint.arswitch.0.pad.6.rxclk_delay_en=1
+# AR8327_CLK_DELAY_SEL1
+hint.arswitch.0.pad.6.txclk_delay_sel=1
+# AR8327_CLK_DELAY_SEL2
+hint.arswitch.0.pad.6.rxclk_delay_sel=2
+
+# XXX there's no LED management just yet!
+hint.arswitch.0.led.ctrl0=0xc737c737
+hint.arswitch.0.led.ctrl1=0x00000000
+hint.arswitch.0.led.ctrl2=0x00000000
+hint.arswitch.0.led.ctrl3=0x00c30c00
+hint.arswitch.0.led.open_drain=0
+
+# force_link=1 is required for the rest of the parameters
+# to be configured.
+hint.arswitch.0.port.0.force_link=1
+hint.arswitch.0.port.0.speed=1000
+hint.arswitch.0.port.0.duplex=1
+hint.arswitch.0.port.0.txpause=1
+hint.arswitch.0.port.0.rxpause=1
+
+# force_link=1 is required for the rest of the parameters
+# to be configured.
+hint.arswitch.0.port.6.force_link=1
+hint.arswitch.0.port.6.speed=1000
+hint.arswitch.0.port.6.duplex=1
+hint.arswitch.0.port.6.txpause=1
+hint.arswitch.0.port.6.rxpause=1
+
+# arge0 - hooked up to AR8327 GMAC6, RGMII
+# set at 1000/full to the switch.
+# so, lock both sides of this connect up to 1000/full;
+# if_arge thus wont change the PLL configuration
+# upon a link status change.
+hint.arge.0.phymask=0x0
+hint.arge.0.miimode=3           # RGMII
+hint.arge.0.media=1000
+hint.arge.0.fduplex=1
+hint.arge.0.pll_1000=0x56000000
+
+# MAC for arge0 is the first 6 bytes of the ART
+hint.arge.0.eeprommac=0x1fff0000
+
+# arge1 - lock up to 1000/full
+hint.arge.1.phymask=0x0
+hint.arge.1.media=1000
+hint.arge.1.fduplex=1
+hint.arge.1.miimode=5		# SGMII
+hint.arge.1.pll_1000=0x03000101
+
+# MAC for arge1 is the second 6 bytes of the ART
+hint.arge.1.eeprommac=0x1fff0006
+
+# ath0: Where the ART is - last 64k in the flash
+hint.ath.0.eepromaddr=0x1fff0000
+hint.ath.0.eepromsize=16384
+
+# ath1: it's different; it's a PCIe attached device, so
+# we instead need to teach the PCIe bridge code about it
+# (ie, the 'early pci fixup' stuff that programs the PCIe
+# host registers on the NIC) and then we teach ath where
+# to find it.
+
+# ath1 hint - pcie slot 0
+# hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff4000
+# hint.pcib.0.bus.0.0.0.ath_fixup_size=16384
+
+# ath0 - eeprom comes from here
+# hint.ath.1.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware"
+
+# Flash layout - the tplink layout differs to what's passed
+# in via the kernel environment.  What's passed in is based on
+# the AP135, but.. well, TP-Link.
+
+# 128 KiB u-boot
+hint.map.0.at="flash/spi0"
+hint.map.0.start=0x00000000
+hint.map.0.end=0x00020000	# 128k u-boot
+hint.map.0.name="u-boot"
+hint.map.0.readonly=1
+
+# Kernel
+hint.map.1.at="flash/spi0"
+hint.map.1.start=0x00020000
+hint.map.1.end="search:0x00020000:0x10000:.!/bin/sh"
+hint.map.1.name="kernel"
+hint.map.1.readonly=1
+
+# Root
+hint.map.2.at="flash/spi0"
+hint.map.2.start="search:0x00020000:0x10000:.!/bin/sh"
+hint.map.2.end=0x007d0000
+hint.map.2.name="rootfs"
+hint.map.2.readonly=1
+
+# 64KiB cfg
+hint.map.4.at="flash/spi0"
+hint.map.4.start=0x00fe0000
+hint.map.4.end=0x00ff0000
+hint.map.4.name="cfg"
+hint.map.4.readonly=0
+
+# 64KiB ART
+hint.map.6.at="flash/spi0"
+hint.map.6.start=0x00ff0000
+hint.map.6.end=0x01000000	# 64k ART
+hint.map.6.name="ART"
+hint.map.6.readonly=1
+
+# TODO: GPIO config
+# These are the GPIO LEDs and buttons which can be software controlled.
+hint.gpio.0.pinmask=0x00600000
+
+# Enable GPIO21, GPIO22 output and high - for USB power
+hint.gpio.0.pinon=0x00600000
+
+# TODO: GPIO pin config:
+# LED_WLAN2G       12
+# BTN_RFKILL       13
+# LED_SYSTEM       14
+# LED_QSS          15
+# BTN_RESET        16
+# LED_WLAN5G       17
+# LED_USB1         18
+# LED_USB2         19
+# USB2_POWER       21
+# USB1_POWER       22
+
+# TODO: PCIe isn't showing link; maybe uboot isn't initialising



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