Date: Fri, 10 Mar 2017 15:30:21 +0100 From: Alexandre Martins <alexandre.martins@stormshield.eu> To: Konstantin Belousov <kostikbel@gmail.com> Cc: freebsd-current <freebsd-current@freebsd.org> Subject: Re: smp_rendezvous_action: Are atomics correctly used ? Message-ID: <1881786.W3Fpph0Tg6@pc-alex> In-Reply-To: <20170310135716.GI16105@kib.kiev.ua> References: <2092905.6A8RAGlt18@pc-alex> <1584060.AQ0HNTQbMq@pc-alex> <20170310135716.GI16105@kib.kiev.ua>
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--nextPart10063405.8zlACVWeQU Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1" Le vendredi 10 mars 2017, 15:57:16 Konstantin Belousov a =E9crit : > On Fri, Mar 10, 2017 at 02:24:52PM +0100, Alexandre Martins wrote: > > Le jeudi 9 mars 2017, 16:25:17 Konstantin Belousov a ?crit : > > > On Thu, Mar 09, 2017 at 02:52:09PM +0100, Alexandre Martins wrote= : > > > > Le jeudi 9 mars 2017, 15:07:54 Konstantin Belousov a ?crit : > > > > > On Thu, Mar 09, 2017 at 10:59:27AM +0100, Alexandre Martins w= rote: > > > > > > I have the save question for the cpu_ipi_pending here: > > > > > >=20 > > > > > > https://svnweb.freebsd.org/base/head/sys/x86/x86/mp_x86.c?v= iew=3Dann > > > > > > otat > > > > > > e#l1 > > > > > > 080> > > > > > >=20 > > > > > > Le jeudi 9 mars 2017, 10:43:14 Alexandre Martins a ?crit : > > > > > > > Hello, > > > > > > >=20 > > > > > > > I'm curently reading the code of the function > > > > > > > smp_rendezvous_action, > > > > > > > in > > > > > > > kern/subr_smp.c file. In that function, i see that the va= riable > > > > > > > smp_rv_waiters is read in some while() loop in a non-atom= ic way. > > > > > > >=20 > > > > > > > https://svnweb.freebsd.org/base/head/sys/kern/subr_smp.c?= view=3Dan > > > > > > > nota > > > > > > > te#l > > > > > > > 412 > > > > > > > https://svnweb.freebsd.org/base/head/sys/kern/subr_smp.c?= view=3Dan > > > > > > > nota > > > > > > > te#l > > > > > > > 458 > > > > > > > https://svnweb.freebsd.org/base/head/sys/kern/subr_smp.c?= view=3Dan > > > > > > > nota > > > > > > > te#l > > > > > > > 472 > > > > > > >=20 > > > > > > > I suspect one of my freeze to be due by that. > > > > >=20 > > > > > You should provide either evidence or, at least, some reasoni= ng > > > > > supporting > > > > > your claims. > > > >=20 > > > > I curently have a software watchdog that triger and does a core= dump. > > > > In > > > > the > > > > coredumps, I always see a CPU trying to write-lock a "rm lock".= Every > > > > time, > > > > that CPU is spinning into the smp_rendezvous_action, in the fir= st > > > > while > > > > loop) while the others are into the idle threads. > > > >=20 > > > > The fact is that freeze is not clear and I start to search "exo= tic" > > > > causes > > > > to explain it. > > >=20 > > > This sounds as the 'usual' deadlock, where some other thread owns= rmlock > > > in > > > read mode. I recommend you to follow the > > > https://www.freebsd.org/doc/en_US.ISO8859-1/books/developers-hand= book/ke > > > rnel debug-deadlocks.html > >=20 > > Just a last question, for my personnal knowledge. > >=20 > > In ARM >=3D 6, for atomic acces, the code should (?) use LDREX and = STREX > > for, I quote : "Use LDREX and STREX to implement interprocess > > communication in multiple-processor and shared-memory systems." (se= e here > > : > > http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.dui04= 89e/Cihbg > > hef.html > In my previous response to you, I explicitely defined what 'atomic' > means when adjected to the term 'load'. The *EX instructions are used= on > ll/sc architectures to implement read/modify/write atomic operations,= > which are different from load (read) operations. Ok ! Because we just want to read the value, there is no need to use th= e *EX=20 version. *EX is intended to be use when a modification will be done the= reafter. >=20 > > But, in that while loop, it's a standard "LDR" that is used. Is it = correct > > too, and why ? >=20 > Which 'that while loop' ? > =09while (atomic_load_acq_int(&smp_rv_waiters[3]) < ncpus) > =09=09cpu_spinwait(); > This one ? No, I point the one at line 412, 458 and 472: 412: while (smp_rv_waiters[0] < smp_rv_ncpus) cpu_spinwait(); 458: while (smp_rv_waiters[1] < smp_rv_ncpus) cpu_spinwait(); 472: while (smp_rv_waiters[2] < smp_rv_ncpus) cpu_spinwait(); >=20 > Because the semantic of the normal load + DMB barrier provides the ex= pected > semantic of atomic_load_acq(), as explained in atomic(9) and utilized= by > the author of the code. So, the writer must use LDREX/STREX to modify the value and use dmb to = make=20 visible to other CPU the write. The readers can read simply the value without the barrier because cache= =20 coherancy protcol will update the value automaticaly. I think I finally got it ! Thank you so much ! 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