Date: Sun, 15 Sep 2013 15:33:44 GMT From: zcore@FreeBSD.org To: svn-soc-all@FreeBSD.org Subject: socsvn commit: r257382 - soc2013/zcore/head/usr.sbin/bhyve Message-ID: <201309151533.r8FFXieE039323@socsvn.freebsd.org>
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Author: zcore Date: Sun Sep 15 15:33:44 2013 New Revision: 257382 URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=257382 Log: s/dprintf/DPRINTF and s/wprintf/WPRINTF also make WPRINTF bugless Modified: soc2013/zcore/head/usr.sbin/bhyve/pci_ahci.c Modified: soc2013/zcore/head/usr.sbin/bhyve/pci_ahci.c ============================================================================== --- soc2013/zcore/head/usr.sbin/bhyve/pci_ahci.c Sun Sep 15 15:32:31 2013 (r257381) +++ soc2013/zcore/head/usr.sbin/bhyve/pci_ahci.c Sun Sep 15 15:33:44 2013 (r257382) @@ -92,11 +92,11 @@ */ #ifdef AHCI_DEBUG static FILE *dbg; -#define dprintf(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0) +#define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0) #else -#define dprintf(format, arg...) +#define DPRINTF(format, arg...) #endif -#define wprintf printf +#define WPRINTF(format, arg...) printf(format, ##arg) struct ahci_ioreq { struct blockif_req io_req; @@ -202,7 +202,7 @@ sc->is |= (1 << i); } - dprintf("%s %x\n", __func__, sc->is); + DPRINTF("%s %x\n", __func__, sc->is); if (sc->is && (sc->ghc & AHCI_GHC_IE)) pci_generate_msi(sc->asc_pi, 0); } @@ -232,7 +232,7 @@ irq = 0; break; default: - wprintf("unsupported fis type %d\n", ft); + WPRINTF("unsupported fis type %d\n", ft); return; } memcpy(p->rfis + offset, fis, len); @@ -919,10 +919,10 @@ { int i; - dprintf("ACMD:"); + DPRINTF("ACMD:"); for (i = 0; i < 16; i++) - dprintf("%02x ", acmd[i]); - dprintf("\n"); + DPRINTF("%02x ", acmd[i]); + DPRINTF("\n"); } switch (acmd[0]) { @@ -1045,7 +1045,7 @@ handle_packet_cmd(p, slot, cfis); break; default: - wprintf("Unsupported cmd:%02x\n", cfis[2]); + WPRINTF("Unsupported cmd:%02x\n", cfis[2]); p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; p->is |= AHCI_P_IX_TFE; p->ci &= ~(1 << slot); @@ -1070,21 +1070,21 @@ 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry)); prdt = (struct ahci_prdt_entry *)(cfis + 0x80); - dprintf("\ncfis:"); + DPRINTF("\ncfis:"); for (i = 0; i < cfl; i++) { if (i % 10 == 0) - dprintf("\n"); - dprintf("%02x ", cfis[i]); + DPRINTF("\n"); + DPRINTF("%02x ", cfis[i]); } - dprintf("\n"); + DPRINTF("\n"); for (i = 0; i < hdr->prdtl; i++) { - dprintf("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba); + DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba); prdt++; } if (cfis[0] != FIS_TYPE_REGH2D) { - wprintf("Not a H2D FIS:%02x\n", cfis[0]); + WPRINTF("Not a H2D FIS:%02x\n", cfis[0]); return; } @@ -1129,7 +1129,7 @@ struct ahci_cmd_hdr *hdr; int ncq = 0; - dprintf("%s %d\n", __func__, err); + DPRINTF("%s %d\n", __func__, err); aior = br->br_param; p = aior->io_pr; @@ -1166,7 +1166,7 @@ STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list); pthread_mutex_unlock(&sc->mtx); - dprintf("%s exit\n", __func__); + DPRINTF("%s exit\n", __func__); } static void @@ -1179,7 +1179,7 @@ struct ahci_ioreq *aior; struct ahci_cmd_hdr *hdr; - dprintf("%s %d\n", __func__, err); + DPRINTF("%s %d\n", __func__, err); aior = br->br_param; p = aior->io_pr; @@ -1208,7 +1208,7 @@ STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list); pthread_mutex_unlock(&sc->mtx); - dprintf("%s exit\n", __func__); + DPRINTF("%s exit\n", __func__); } @@ -1340,7 +1340,7 @@ offset = (offset - AHCI_OFFSET) % AHCI_STEP; struct ahci_port *p = &sc->port[port]; - dprintf("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", + DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", port, offset, value); switch (offset) { case AHCI_P_CLB: @@ -1401,7 +1401,7 @@ case AHCI_P_TFD: case AHCI_P_SIG: case AHCI_P_SSTS: - wprintf("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset); + WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset); break; case AHCI_P_SCTL: if (!(p->cmd & AHCI_P_CMD_ST)) { @@ -1430,7 +1430,7 @@ static void pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) { - dprintf("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", + DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", offset, value); switch (offset) { @@ -1438,7 +1438,7 @@ case AHCI_PI: case AHCI_VS: case AHCI_CAP2: - wprintf("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset); + WPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset); break; case AHCI_GHC: if (value & AHCI_GHC_HR) @@ -1473,7 +1473,7 @@ else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) pci_ahci_port_write(sc, offset, value); else - wprintf("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset); + WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset); pthread_mutex_unlock(&sc->mtx); } @@ -1504,7 +1504,7 @@ value = 0; break; } - dprintf("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n", + DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n", offset, value); return (value); @@ -1544,7 +1544,7 @@ value = 0; break; } - dprintf("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n", + DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n", port, offset, value); return value; @@ -1568,7 +1568,7 @@ value = pci_ahci_port_read(sc, offset); else { value = 0; - wprintf("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset); + WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset); } pthread_mutex_unlock(&sc->mtx);
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