Date: Fri, 24 Feb 2006 17:57:48 GMT From: Kip Macy <kmacy@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 92350 for review Message-ID: <200602241757.k1OHvmMi013013@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=92350 Change 92350 by kmacy@kmacy_storage:sun4v_work on 2006/02/24 17:57:18 switch over to new scratch accessor macros load_dw was faulting on storing to o2 for no apparent reason add save/restore to helper function Affected files ... .. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/exception.S#10 edit .. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/locore.S#5 edit .. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/support.S#5 edit .. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/swtch.S#5 edit Differences ... ==== //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/exception.S#10 (text+ko) ==== @@ -69,7 +69,6 @@ #include "assym.s" -#include <sun4v/sun4v/wbuf.S> #define TSB_KERNEL_MASK 0x0 #define TSB_KERNEL 0x0 @@ -79,6 +78,12 @@ .register %g6,#ignore .register %g7,#ignore + +#define PCB_REG %g6 + +#include <sun4v/sun4v/wbuf.S> + + /* * Atomically set the reference bit in a tte. */ @@ -94,13 +99,6 @@ #define TTE_SET_REF(r1, r2, r3) TTE_SET_BIT(r1, r2, r3, TD_REF) #define TTE_SET_W(r1, r2, r3) TTE_SET_BIT(r1, r2, r3, TD_W) -#define LOAD_ALT \ - mov SCRATCH_REG_PCPU, %g0 ; \ - ldxa [%g0]ASI_SCRATCHPAD, PCPU_REG ; \ - mov SCRATCH_REG_PCB, %g0 ; \ - ldxa [%g0]ASI_SCRATCHPAD, PCB_REG - - /* * Macros for spilling and filling live windows. @@ -461,13 +459,16 @@ tl0_gen T_RESERVED .endr .endm + + .macro tl1_split #if 0 - .macro tl1_split rdpr %wstate, %g1 wrpr %g1, WSTATE_NESTED, %wstate save %sp, -(CCFSZ + TF_SIZEOF), %sp +#endif + nop .endm -#endif + .macro tl1_setup type tl1_split clr %o1 @@ -483,49 +484,67 @@ .macro tl1_reserved count .rept \count -#if 0 tl1_gen T_RESERVED -#endif .endr .endm .macro insn_excptn + nop .align 32 .endm .macro insn_miss + nop + mov %o0, %g6 + mov 0x23, %o0 + call hv_cnputchar + mov 0x24, %o0 + call hv_cnputchar .align 32 .endm .macro data_excptn + nop .align 32 .endm .macro data_miss + nop + mov %o0, %g6 + mov 0x23, %o0 + call hv_cnputchar + mov 0x24, %o0 + call hv_cnputchar .align 32 .endm .macro data_prot + nop .align 32 .endm .macro tl0_align + nop .align 32 .endm .macro cpu_mondo + nop .align 32 .endm .macro dev_mondo + nop .align 32 .endm .macro resumable_error + nop .align 32 .endm .macro nonresumable_error + nop .align 32 .endm @@ -581,7 +600,7 @@ retry ; \ .skip (31-25)*4 ; \ ba,a,pt %xcc, fault_64bit_##target ; \ - + .align 128 .macro spill_32bit_primary_sn0 spill_32bit_asi(ASI_AIUP, sn0) @@ -604,6 +623,11 @@ .endm .macro spill_64bit_nucleus_not + mov %o0, %g6 + mov 0x23, %o0 + call hv_cnputchar + mov 0x24, %o0 + call hv_cnputchar spill_64bit_asi(ASI_N,not) .endm @@ -628,6 +652,11 @@ .endm .macro fill_64bit_nucleus_not + mov %o0, %g6 + mov 0x23, %o0 + call hv_cnputchar + mov 0x24, %o0 + call hv_cnputchar fill_64bit_asi(ASI_N, not) .endm @@ -672,10 +701,12 @@ .endm .macro spill_mixed + nop .align 128 .endm .macro fill_mixed + nop .align 128 .endm @@ -729,6 +760,7 @@ .endm .macro tl0_immu_miss + nop .align 128 .endm @@ -1197,11 +1229,13 @@ nop .align 32 .endm + +ENTRY(tl0_fp_restore) + GET_PCB(PCB_REG) -ENTRY(tl0_fp_restore) - ldx [PCB_REG + PCB_FLAGS], %g1 + ldx [%g6 + PCB_FLAGS], %g1 andn %g1, PCB_FEF, %g1 - stx %g1, [PCB_REG + PCB_FLAGS] + stx %g1, [%g6 + PCB_FLAGS] wr %g0, FPRS_FEF, %fprs wr %g0, ASI_BLK_S, %asi @@ -1241,6 +1275,7 @@ bgeu,a,pn %xcc, 1f nop + GET_PCB(PCB_REG) wr %g0, FPRS_FEF, %fprs wr %g0, ASI_BLK_S, %asi ldda [PCB_REG + PCB_KFP + (0 * 64)] %asi, %f0 @@ -1666,7 +1701,7 @@ .sect .trap .align 0x8000 - .globl tl0_base + .globl tl0_base,tl0_insn_miss, tl0_insn_excptn, tl0_spill_n_normal tl0_base: tl0_reserved 8 ! 0x0-0x7 tl0_insn_excptn: @@ -1829,6 +1864,8 @@ tl1_reserved 32 ! 0x2c0-0x2df tl1_fill_n_other: tl1_reserved 32 ! 0x2e0-0x2ff +.globl tl0_end +tl0_end: /* * no discretionary traps at TL 1 - leaving us with a 24k trap table */ @@ -1901,8 +1938,10 @@ * user traps, which implies that the condition that caused the trap * in the first place is still valid, so it will occur again when we * re-execute the trapping instruction. - */ + */ +#if 0 ldx [PCB_REG + PCB_NSAVED], %l1 +#endif brnz,a,pn %l1, tl0_trap mov T_SPILL, %o0 @@ -1917,10 +1956,12 @@ rd %fprs, %l1 or %l1, FPRS_FEF, %l2 wr %l2, 0, %fprs +#if 0 dec 8, ASP_REG stx %fsr, [ASP_REG] ldx [ASP_REG], %l4 inc 8, ASP_REG +#endif wr %l1, 0, %fprs rdpr %tstate, %l5 @@ -1980,7 +2021,7 @@ * of cpu migration and using the wrong pcpup. */ ENTRY(tl0_trap) - LOAD_ALT + GET_PCB(PCB_REG) rdpr %tstate, %l0 rdpr %tpc, %l1 @@ -2038,7 +2079,7 @@ mov PCPU_REG, %l1 wrpr %g0, PSTATE_NORMAL, %pstate - stx %g6, [%sp + SPOFF + CCFSZ + TF_G6] + stx PCB_REG, [%sp + SPOFF + CCFSZ + TF_G6] stx %g7, [%sp + SPOFF + CCFSZ + TF_G7] mov %l0, PCB_REG @@ -2069,7 +2110,7 @@ * void tl0_intr(u_int level, u_int mask) */ ENTRY(tl0_intr) - LOAD_ALT + GET_PCB(PCB_REG) rdpr %tstate, %l0 rdpr %tpc, %l1 @@ -2228,7 +2269,9 @@ * spilled to the pcb, they will not be copied out and the stack will * be inconsistent. */ +#if 0 1: ldx [PCB_REG + PCB_NSAVED], %l1 +#endif brz,a,pt %l1, 2f nop wrpr %g0, 0, %pil @@ -2284,8 +2327,9 @@ * Switch to alternate globals. This frees up some registers we * can use after the restore changes our window. */ +#if 0 LOAD_ALT - +#endif /* * Drop %pil to zero. It must have been zero at the time of the * trap, since we were in usermode, but it was raised above in @@ -2438,7 +2482,7 @@ * kernel. We clobbered them above restoring the user's globals * so this is very important. */ - LOAD_ALT + GET_PCB(PCB_REG) mov PCB_REG, %o0 mov PCPU_REG, %o1 wrpr %g0, PSTATE_NORMAL, %pstate @@ -2571,8 +2615,10 @@ ldx [%sp + SPOFF + CCFSZ + TF_G6], %g6 ldx [%sp + SPOFF + CCFSZ + TF_G7], %g7 -1: LOAD_ALT - +1: +#if 0 + LOAD_ALT +#endif andn %l0, TSTATE_CWP_MASK, %g1 mov %l1, %g2 mov %l2, %g3 @@ -2704,9 +2750,9 @@ ldx [%sp + SPOFF + CCFSZ + TF_G3], %g3 ldx [%sp + SPOFF + CCFSZ + TF_G4], %g4 ldx [%sp + SPOFF + CCFSZ + TF_G5], %g5 - +#if 0 LOAD_ALT - +#endif andn %l0, TSTATE_CWP_MASK, %g1 mov %l1, %g2 mov %l2, %g3 ==== //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/locore.S#5 (text+ko) ==== @@ -79,7 +79,7 @@ /* * Get onto thread0's kstack. */ - sub PCB_REG, SPOFF + CCFSZ, %sp + sub %g6, SPOFF + CCFSZ, %sp /* * And away we go. This doesn't return. @@ -105,7 +105,7 @@ * Normal %g6 points to the current thread's pcb, and %g7 points to * the per-cpu data structure. */ - mov %o1, PCB_REG + mov %o1, %g6 mov %o0, PCPU_REG /* @@ -116,7 +116,7 @@ mov SCRATCH_REG_PCPU, %g1 stxa PCPU_REG, [%g1]ASI_SCRATCHPAD mov SCRATCH_REG_PCB, %g1 - stxa PCB_REG, [%g1]ASI_SCRATCHPAD + stxa %g6, [%g1]ASI_SCRATCHPAD retl nop ==== //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/support.S#5 (text+ko) ==== @@ -679,10 +679,13 @@ */ ENTRY(load_real_dw) - ldda [%g0 + %o0]ASI_LDTD_REAL, %o0 - stx %o0, [%o1] + save %sp, -SA(MINFRAME64), %sp + ldda [%g0 + %i0]ASI_LDTD_REAL, %l0 + stx %l0, [%i1] + stx %l1, [%i2] + restore retl - stx %o1, [%o2] + nop END(load_real_dw) /* @@ -741,8 +744,35 @@ retl nop END(invltlb) + +! %o0 = pa +! %o1 = size +ENTRY(bzerophyspage) + save %sp, -SA(MINFRAME64), %sp + mov 8, %l1 + mov 16, %l2 + mov 24, %l3 + mov 32, %l4 + mov 40, %l5 + mov 48, %l6 + mov 56, %l7 +1: stxa %g0, [%i0]ASI_REAL + stxa %g0, [%i0 + %l1]ASI_REAL + stxa %g0, [%i0 + %l2]ASI_REAL + stxa %g0, [%i0 + %l3]ASI_REAL + stxa %g0, [%i0 + %l4]ASI_REAL + stxa %g0, [%i0 + %l5]ASI_REAL + stxa %g0, [%i0 + %l6]ASI_REAL + stxa %g0, [%i0 + %l7]ASI_REAL + sub %i1, 64, %i1 + brnz,pt %i1, 1b + add %i0, 64, %i0 + membar #Sync + retl + restore +END(bzerophyspage) #ifdef GPROF ==== //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/swtch.S#5 (text+ko) ==== @@ -37,6 +37,9 @@ .register %g2, #ignore .register %g3, #ignore +#define PCB_REG %g6 + + /* * void cpu_throw(struct thread *old, struct thread *new) */ @@ -51,6 +54,7 @@ * void cpu_switch(struct thread *old, struct thread *new) */ ENTRY(cpu_switch) + GET_PCB(PCB_REG) save %sp, -CCFSZ, %sp mov %i1, %i0
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