Date: Wed, 14 Aug 2019 16:54:51 +0000 (UTC) From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r351032 - stable/12/sys/arm64/arm64 Message-ID: <201908141654.x7EGspd4045904@repo.freebsd.org>
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Author: andrew Date: Wed Aug 14 16:54:51 2019 New Revision: 351032 URL: https://svnweb.freebsd.org/changeset/base/351032 Log: MFC r345510: Sort printing of the ID registers on arm64 to be identical to the documentation. This will simplify checking new fields when they are added. Modified: stable/12/sys/arm64/arm64/identcpu.c Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/arm64/arm64/identcpu.c ============================================================================== --- stable/12/sys/arm64/arm64/identcpu.c Wed Aug 14 16:45:16 2019 (r351031) +++ stable/12/sys/arm64/arm64/identcpu.c Wed Aug 14 16:54:51 2019 (r351032) @@ -478,63 +478,68 @@ print_cpu_features(u_int cpu) printed = 0; sbuf_printf(sb, " Instruction Set Attributes 0 = <"); - switch (ID_AA64ISAR0_RDM(cpu_desc[cpu].id_aa64isar0)) { - case ID_AA64ISAR0_RDM_NONE: + switch (ID_AA64ISAR0_DP(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_DP_NONE: break; - case ID_AA64ISAR0_RDM_IMPL: - sbuf_printf(sb, "%sRDM", SEP_STR); + case ID_AA64ISAR0_DP_IMPL: + sbuf_printf(sb, "%sDotProd", SEP_STR); break; default: - sbuf_printf(sb, "%sUnknown RDM", SEP_STR); + sbuf_printf(sb, "%sUnknown DP", SEP_STR); + break; } - switch (ID_AA64ISAR0_ATOMIC(cpu_desc[cpu].id_aa64isar0)) { - case ID_AA64ISAR0_ATOMIC_NONE: + switch (ID_AA64ISAR0_SM4(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_SM4_NONE: break; - case ID_AA64ISAR0_ATOMIC_IMPL: - sbuf_printf(sb, "%sAtomic", SEP_STR); + case ID_AA64ISAR0_SM4_IMPL: + sbuf_printf(sb, "%sSM4", SEP_STR); break; default: - sbuf_printf(sb, "%sUnknown Atomic", SEP_STR); + sbuf_printf(sb, "%sUnknown SM4", SEP_STR); + break; } - switch (ID_AA64ISAR0_AES(cpu_desc[cpu].id_aa64isar0)) { - case ID_AA64ISAR0_AES_NONE: + switch (ID_AA64ISAR0_SM3(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_SM3_NONE: break; - case ID_AA64ISAR0_AES_BASE: - sbuf_printf(sb, "%sAES", SEP_STR); + case ID_AA64ISAR0_SM3_IMPL: + sbuf_printf(sb, "%sSM3", SEP_STR); break; - case ID_AA64ISAR0_AES_PMULL: - sbuf_printf(sb, "%sAES+PMULL", SEP_STR); - break; default: - sbuf_printf(sb, "%sUnknown AES", SEP_STR); + sbuf_printf(sb, "%sUnknown SM3", SEP_STR); break; } - switch (ID_AA64ISAR0_SHA1(cpu_desc[cpu].id_aa64isar0)) { - case ID_AA64ISAR0_SHA1_NONE: + switch (ID_AA64ISAR0_SHA3(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_SHA3_NONE: break; - case ID_AA64ISAR0_SHA1_BASE: - sbuf_printf(sb, "%sSHA1", SEP_STR); + case ID_AA64ISAR0_SHA3_IMPL: + sbuf_printf(sb, "%sSHA3", SEP_STR); break; default: - sbuf_printf(sb, "%sUnknown SHA1", SEP_STR); + sbuf_printf(sb, "%sUnknown SHA3", SEP_STR); break; } - switch (ID_AA64ISAR0_SHA2(cpu_desc[cpu].id_aa64isar0)) { - case ID_AA64ISAR0_SHA2_NONE: + switch (ID_AA64ISAR0_RDM(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_RDM_NONE: break; - case ID_AA64ISAR0_SHA2_BASE: - sbuf_printf(sb, "%sSHA2", SEP_STR); + case ID_AA64ISAR0_RDM_IMPL: + sbuf_printf(sb, "%sRDM", SEP_STR); break; - case ID_AA64ISAR0_SHA2_512: - sbuf_printf(sb, "%sSHA2+SHA512", SEP_STR); - break; default: - sbuf_printf(sb, "%sUnknown SHA2", SEP_STR); + sbuf_printf(sb, "%sUnknown RDM", SEP_STR); + } + + switch (ID_AA64ISAR0_ATOMIC(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_ATOMIC_NONE: break; + case ID_AA64ISAR0_ATOMIC_IMPL: + sbuf_printf(sb, "%sAtomic", SEP_STR); + break; + default: + sbuf_printf(sb, "%sUnknown Atomic", SEP_STR); } switch (ID_AA64ISAR0_CRC32(cpu_desc[cpu].id_aa64isar0)) { @@ -548,47 +553,42 @@ print_cpu_features(u_int cpu) break; } - switch (ID_AA64ISAR0_SHA3(cpu_desc[cpu].id_aa64isar0)) { - case ID_AA64ISAR0_SHA3_NONE: + switch (ID_AA64ISAR0_SHA2(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_SHA2_NONE: break; - case ID_AA64ISAR0_SHA3_IMPL: - sbuf_printf(sb, "%sSHA3", SEP_STR); + case ID_AA64ISAR0_SHA2_BASE: + sbuf_printf(sb, "%sSHA2", SEP_STR); break; - default: - sbuf_printf(sb, "%sUnknown SHA3", SEP_STR); + case ID_AA64ISAR0_SHA2_512: + sbuf_printf(sb, "%sSHA2+SHA512", SEP_STR); break; - } - - switch (ID_AA64ISAR0_SM3(cpu_desc[cpu].id_aa64isar0)) { - case ID_AA64ISAR0_SM3_NONE: - break; - case ID_AA64ISAR0_SM3_IMPL: - sbuf_printf(sb, "%sSM3", SEP_STR); - break; default: - sbuf_printf(sb, "%sUnknown SM3", SEP_STR); + sbuf_printf(sb, "%sUnknown SHA2", SEP_STR); break; } - switch (ID_AA64ISAR0_SM4(cpu_desc[cpu].id_aa64isar0)) { - case ID_AA64ISAR0_SM4_NONE: + switch (ID_AA64ISAR0_SHA1(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_SHA1_NONE: break; - case ID_AA64ISAR0_SM4_IMPL: - sbuf_printf(sb, "%sSM4", SEP_STR); + case ID_AA64ISAR0_SHA1_BASE: + sbuf_printf(sb, "%sSHA1", SEP_STR); break; default: - sbuf_printf(sb, "%sUnknown SM4", SEP_STR); + sbuf_printf(sb, "%sUnknown SHA1", SEP_STR); break; } - switch (ID_AA64ISAR0_DP(cpu_desc[cpu].id_aa64isar0)) { - case ID_AA64ISAR0_DP_NONE: + switch (ID_AA64ISAR0_AES(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_AES_NONE: break; - case ID_AA64ISAR0_DP_IMPL: - sbuf_printf(sb, "%sDotProd", SEP_STR); + case ID_AA64ISAR0_AES_BASE: + sbuf_printf(sb, "%sAES", SEP_STR); break; + case ID_AA64ISAR0_AES_PMULL: + sbuf_printf(sb, "%sAES+PMULL", SEP_STR); + break; default: - sbuf_printf(sb, "%sUnknown DP", SEP_STR); + sbuf_printf(sb, "%sUnknown AES", SEP_STR); break; } @@ -852,17 +852,6 @@ print_cpu_features(u_int cpu) break; } - switch (ID_AA64MMFR0_TGRAN16(cpu_desc[cpu].id_aa64mmfr0)) { - case ID_AA64MMFR0_TGRAN16_NONE: - break; - case ID_AA64MMFR0_TGRAN16_IMPL: - sbuf_printf(sb, "%s16k Granule", SEP_STR); - break; - default: - sbuf_printf(sb, "%sUnknown 16k Granule", SEP_STR); - break; - } - switch (ID_AA64MMFR0_TGRAN64(cpu_desc[cpu].id_aa64mmfr0)) { case ID_AA64MMFR0_TGRAN64_NONE: break; @@ -874,14 +863,14 @@ print_cpu_features(u_int cpu) break; } - switch (ID_AA64MMFR0_BIGEND(cpu_desc[cpu].id_aa64mmfr0)) { - case ID_AA64MMFR0_BIGEND_FIXED: + switch (ID_AA64MMFR0_TGRAN16(cpu_desc[cpu].id_aa64mmfr0)) { + case ID_AA64MMFR0_TGRAN16_NONE: break; - case ID_AA64MMFR0_BIGEND_MIXED: - sbuf_printf(sb, "%sMixedEndian", SEP_STR); + case ID_AA64MMFR0_TGRAN16_IMPL: + sbuf_printf(sb, "%s16k Granule", SEP_STR); break; default: - sbuf_printf(sb, "%sUnknown Endian switching", SEP_STR); + sbuf_printf(sb, "%sUnknown 16k Granule", SEP_STR); break; } @@ -904,6 +893,17 @@ print_cpu_features(u_int cpu) break; default: sbuf_printf(sb, "%sUnknown S/NS Mem", SEP_STR); + break; + } + + switch (ID_AA64MMFR0_BIGEND(cpu_desc[cpu].id_aa64mmfr0)) { + case ID_AA64MMFR0_BIGEND_FIXED: + break; + case ID_AA64MMFR0_BIGEND_MIXED: + sbuf_printf(sb, "%sMixedEndian", SEP_STR); + break; + default: + sbuf_printf(sb, "%sUnknown Endian switching", SEP_STR); break; }
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