Date: Thu, 12 Sep 1996 11:12:53 -0700 (MST) From: Terry Lambert <terry@lambert.org> To: smp@csn.net (Steve Passe) Cc: peter@spinner.dialix.com, rv@groa.uct.ac.za, freebsd-smp@freebsd.org Subject: Re: Intel XXpress - some SMP benchmarks Message-ID: <199609121812.LAA07189@phaeton.artisoft.com> In-Reply-To: <199609120812.CAA15528@clem.systemsix.com> from "Steve Passe" at Sep 12, 96 02:12:56 am
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> > Hint: ALL the APIC ID registers are read/write. > > > > Can you see it yet? :-) > > we tried that on the XXPRESS and (Russel, please confirm this) an instant > reset of the hardware. Any chance that a write of the ID register acts as an INIT IPI? That's what seems to be implied. I suspect that you will need to inventory the processors, then back-fill the holes for the case where you would get an ID collision during the shuffling -- ie: if I have n processors, all APIC ID's < (n-1) are left alone, and only the remainder are rewritten. I *believe* that the BP is guranteed an APIC ID of 0. You may want to disassemble your MP cold boot BIOS code to see about the ID assignment; clearly it must be happening in BIOS in any case, since the PPRO's are "glueless" and would care about which slots they are put in, otherwise. Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers.
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