Date: Fri, 10 Mar 2017 16:23:02 +0100 From: Alexandre Martins <alexandre.martins@stormshield.eu> To: Konstantin Belousov <kostikbel@gmail.com> Cc: freebsd-current <freebsd-current@freebsd.org> Subject: Re: smp_rendezvous_action: Are atomics correctly used ? Message-ID: <2689552.NsBHWcFoDC@pc-alex> In-Reply-To: <20170310144626.GL16105@kib.kiev.ua> References: <2092905.6A8RAGlt18@pc-alex> <1881786.W3Fpph0Tg6@pc-alex> <20170310144626.GL16105@kib.kiev.ua>
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--nextPart1654324.CXniCo5d1m Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1" Le vendredi 10 mars 2017, 16:46:26 Konstantin Belousov a =E9crit : > On Fri, Mar 10, 2017 at 03:30:21PM +0100, Alexandre Martins wrote: > > Le vendredi 10 mars 2017, 15:57:16 Konstantin Belousov a ?crit : > > > On Fri, Mar 10, 2017 at 02:24:52PM +0100, Alexandre Martins wrote= : > > > > Le jeudi 9 mars 2017, 16:25:17 Konstantin Belousov a ?crit : > > > > > On Thu, Mar 09, 2017 at 02:52:09PM +0100, Alexandre Martins w= rote: > > > > > > Le jeudi 9 mars 2017, 15:07:54 Konstantin Belousov a ?crit = : > > > > > > > On Thu, Mar 09, 2017 at 10:59:27AM +0100, Alexandre Marti= ns=20 wrote: > > > > > > > > I have the save question for the cpu_ipi_pending here: > > > > > > > >=20 > > > > > > > > https://svnweb.freebsd.org/base/head/sys/x86/x86/mp_x86= .c?view > > > > > > > > =3Dann > > > > > > > > otat > > > > > > > > e#l1 > > > > > > > > 080> > > > > > > > >=20 > > > > > > > > Le jeudi 9 mars 2017, 10:43:14 Alexandre Martins a ?cri= t : > > > > > > > > > Hello, > > > > > > > > >=20 > > > > > > > > > I'm curently reading the code of the function > > > > > > > > > smp_rendezvous_action, > > > > > > > > > in > > > > > > > > > kern/subr_smp.c file. In that function, i see that th= e > > > > > > > > > variable > > > > > > > > > smp_rv_waiters is read in some while() loop in a non-= atomic > > > > > > > > > way. > > > > > > > > >=20 > > > > > > > > > https://svnweb.freebsd.org/base/head/sys/kern/subr_sm= p.c?vie > > > > > > > > > w=3Dan > > > > > > > > > nota > > > > > > > > > te#l > > > > > > > > > 412 > > > > > > > > > https://svnweb.freebsd.org/base/head/sys/kern/subr_sm= p.c?vie > > > > > > > > > w=3Dan > > > > > > > > > nota > > > > > > > > > te#l > > > > > > > > > 458 > > > > > > > > > https://svnweb.freebsd.org/base/head/sys/kern/subr_sm= p.c?vie > > > > > > > > > w=3Dan > > > > > > > > > nota > > > > > > > > > te#l > > > > > > > > > 472 > > > > > > > > >=20 > > > > > > > > > I suspect one of my freeze to be due by that. > > > > > > >=20 > > > > > > > You should provide either evidence or, at least, some rea= soning > > > > > > > supporting > > > > > > > your claims. > > > > > >=20 > > > > > > I curently have a software watchdog that triger and does a > > > > > > coredump. > > > > > > In > > > > > > the > > > > > > coredumps, I always see a CPU trying to write-lock a "rm lo= ck". > > > > > > Every > > > > > > time, > > > > > > that CPU is spinning into the smp_rendezvous_action, in the= first > > > > > > while > > > > > > loop) while the others are into the idle threads. > > > > > >=20 > > > > > > The fact is that freeze is not clear and I start to search > > > > > > "exotic" > > > > > > causes > > > > > > to explain it. > > > > >=20 > > > > > This sounds as the 'usual' deadlock, where some other thread = owns > > > > > rmlock > > > > > in > > > > > read mode. I recommend you to follow the > > > > > https://www.freebsd.org/doc/en_US.ISO8859-1/books/developers-= handboo > > > > > k/ke > > > > > rnel debug-deadlocks.html > > > >=20 > > > > Just a last question, for my personnal knowledge. > > > >=20 > > > > In ARM >=3D 6, for atomic acces, the code should (?) use LDREX = and STREX > > > > for, I quote : "Use LDREX and STREX to implement interprocess > > > > communication in multiple-processor and shared-memory systems."= (see > > > > here > > > >=20 > > > > http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.d= ui0489e/C > > > > ihbg > > > > hef.html > > >=20 > > > In my previous response to you, I explicitely defined what 'atomi= c' > > > means when adjected to the term 'load'. The *EX instructions are = used on > > > ll/sc architectures to implement read/modify/write atomic operati= ons, > > > which are different from load (read) operations. > >=20 > > Ok ! Because we just want to read the value, there is no need to us= e the > > *EX version. *EX is intended to be use when a modification will be = done > > thereafter.>=20 > > > > But, in that while loop, it's a standard "LDR" that is used. Is= it > > > > correct > > > > too, and why ? > > >=20 > > > Which 'that while loop' ? > > >=20 > > > =09while (atomic_load_acq_int(&smp_rv_waiters[3]) < ncpus) > > > =09 > > > =09=09cpu_spinwait(); > > >=20 > > > This one ? > >=20 > > No, I point the one at line 412, 458 and 472: > >=20 > > 412: while (smp_rv_waiters[0] < smp_rv_ncpus) > >=20 > > cpu_spinwait(); > >=20 > > 458: while (smp_rv_waiters[1] < smp_rv_ncpus) > >=20 > > cpu_spinwait(); > >=20 > > 472: while (smp_rv_waiters[2] < smp_rv_ncpus) > >=20 > > cpu_spinwait(); > > >=20 > > > Because the semantic of the normal load + DMB barrier provides th= e > > > expected > > > semantic of atomic_load_acq(), as explained in atomic(9) and util= ized by > > > the author of the code. > >=20 > > So, the writer must use LDREX/STREX to modify the value and use dmb= to > > make > > visible to other CPU the write. >=20 > No, this is false statement on all/many counts. ll/sc is only needed= for > atomic modification, not for a write. If you need to assign a given = value > to the variable, STR instruction does just that. LDREX/STREX provide= a > way to ensure that a modification done atomically. E.g., if your int= ent > is to add 1 to the word in memory, you need to ensure that the memory= > is not modified, when writing out the modified read value. >=20 > Next, DMB does not 'make visible' the modification. DMB separates > externally visible effects of executed instructions before and after = it. > From the whole guarantees provided by this separation, atomic_load_ac= q() > only needs the effect of not allowing later memory accesses to occur > earlier than the DMB instruction was executed (the acquire semantic).= > ARMv8 provides loads and stores with the reduced barriers to implemen= t > _acq/_rel without excess overhead of full barrier. >=20 > DMB does not make any store instruction more effective than it alread= y is. OK, that why I didn't understand well the use of atomics. It's related to the function "atomic_load_xxx/atomic_store_xxx" that ma= de me=20 think that it's THIS store or THIS load is atomic, but no. The loads an= d=20 stores are already atomic. Thoses functions just do a barrier (if neede= d)=20 before for "acq" and after for the "rel". The barrier does not "flush" = anything=20 in memory but prevent loads and stores reordering. I realy need to practice more the use of atomic _correctly_ (^_^) >=20 > > The readers can read simply the value without the barrier because c= ache > > coherancy protcol will update the value automaticaly. >=20 > Same is true for stores. This is why plain loads and stores are atom= ic. >=20 > > I think I finally got it ! > > Thank you so much ! > >=20 > > Best regards, =2D-=20 Alexandre Martins STORMSHIELD --nextPart1654324.CXniCo5d1m Content-Type: application/pkcs7-signature; name="smime.p7s" Content-Disposition: attachment; filename="smime.p7s" Content-Transfer-Encoding: base64 MIAGCSqGSIb3DQEHAqCAMIACAQExDzANBglghkgBZQMEAgEFADCABgkqhkiG9w0BBwEAAKCCCOUw ggSGMIICbqADAgECAgUA28zw7TANBgkqhkiG9w0BAQsFADBIMQswCQYDVQQGEwJGUjEUMBIGA1UE CgwLU1RPUk1TSElFTEQxIzAhBgNVBAMMGlN0b3Jtc2hpZWxkIFJvb3QgQXV0aG9yaXR5MB4XDTE0 MDkwNDE1MDcxMFoXDTI0MDkwMTE1MDcxMFowSTELMAkGA1UEBhMCRlIxFDASBgNVBAoMC1NUT1JN U0hJRUxEMSQwIgYDVQQDDBtTdG9ybXNoaWVsZCBVc2VycyBBdXRob3JpdHkwggEiMA0GCSqGSIb3 DQEBAQUAA4IBDwAwggEKAoIBAQDChwWgC/6VWKL7jgWI3eA2sVvRdOwuHcXsRAAXVWdlMC0ygg7u 45E78GhAnpdl8QbIu7x/Q2zOq6KttspwDEIjkoMLTZngLLlGjYJZPfuSoC6hl9R7vRd5f8Fhu3v0 xQ/7vzKYz4C836IGCrk31gmrPO0H0fxkyxCMfhoTTzue3oXW1IsmQwCrOPOu2Y82QANDhbifWLjI WJetnj58YRKR82KBs3Flbqxtp0mi9+IswMvCCRSoT+ORB73Cl6URt7Qm7BcD+qnkJ9uwlUC94dIl T2hX4ybY/w/ssA17Ew418fgyRCWQXzgjZgZ/XUcw2WP9dIggA7Pg+c/xeROJH1zvAgMBAAGjdjB0 MB0GA1UdDgQWBBShbYRsooCFBXx8dXWANMETW5fXgTAfBgNVHSMEGDAWgBS4Qqn6Z0Twf9NhjOyl x1CutL3sozAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQEAwIBBjARBglghkgBhvhCAQEEBAMC AQYwDQYJKoZIhvcNAQELBQADggIBAE6C9zkt2J6dPm2KLbzRS6rBIYZNFi0X59g3ekQ2Sc4UWsq+ B3L86j5xnQSRnIM/DKV1+Q2UHbU/qsh4cto2fwTV6V+aJ07Vu/bJE1rAN4AI4V26ytf7VoBcBjVZ Jq8pHOMp/G2eQH7F1xqzml68DpKku66aUalkcC9IM82m7AW3YAyvDoYEAchv4qyL8qhVLLp6LNru 8ZOhMELhZLWl4ulw/SFDMhcBS6I4wC6icj71MLGSrr61vMktMdwQ+CGFQ5z5JbaxM61VgzKay8+g lw+xTbpnitrDfhkzHs2fdwOOur3vtNnNsrdBWiYPseJ2k4VGD7ov5kITQZckmZyF/V+Ir//agJQG VuwhDZCXgXOvrje+FLYp7tQ9pgSvLbluh1A+ywfyHnFI4n6tZy9SD3MIDgWR4KwFLM1Qmt3NQb32 tkq9Vm0jUcQXFfbnWKLA9krw3m8NmCqhL5PzpfOegYOc0QJWfMQamxeWxXMLk6uKisS//+VqfpCa 5Jx53t+9DmoN1+ob4jOprPaX6tfBBr5djah2yzPGjHEB52VgWXxIF9lCM2z7Qw+zFb2PIdNeSjIk NEFg/1orKAAa5gQXAQynN2J7E+aLf2XLhHcS0v+9yoisPEw9+Tb5F1uQh+gzYD5JUUYcYWncnX8g P8k6X+F5mQ/81IoNL/IejxJgy/LoMIIEVzCCAz+gAwIBAgIFAIUoy7swDQYJKoZIhvcNAQELBQAw STELMAkGA1UEBhMCRlIxFDASBgNVBAoMC1NUT1JNU0hJRUxEMSQwIgYDVQQDDBtTdG9ybXNoaWVs ZCBVc2VycyBBdXRob3JpdHkwHhcNMTYwOTAxMTUxMTA4WhcNMTcwOTAxMTUxMTA4WjBwMQswCQYD VQQGEwJGUjEUMBIGA1UECgwLU1RPUk1TSElFTEQxGjAYBgNVBAMMEUFsZXhhbmRyZSBNQVJUSU5T MS8wLQYJKoZIhvcNAQkBFiBhbGV4YW5kcmUubWFydGluc0BzdG9ybXNoaWVsZC5ldTCCASIwDQYJ KoZIhvcNAQEBBQADggEPADCCAQoCggEBAMN+CnvE13jKEwJ+OyMzwBpC02dY+LpD5luJwnJTVnV2 9aUjEMI+xGFMMHd9kSIVInbk4WDe1ELOKerg0dzgnkRiOHECSGum1UhcZABxQgY2cmSffNQ6JVro 52UaBlt3aTOk3imYJCHUIGgOWMvOtRc8BxyBHdi15FZPj/F9I+AKufRFsBXUakplFIAPEwy3m2eR a/eCMLqGJUyK7YmsAlEnYn2mA38zIoqtKvL6KPHtrV8fw1SRLQ13+j9nu1LlCaqhmLtILFxhV0/9 uDTvx5cKtZ8Xj1nPM6NUUrso9qlXwm4On6Y34pVTtnYGMQRuljil3Hiz84RJjPDJYRGwbgkCAwEA AaOCAR0wggEZMB0GA1UdDgQWBBTmRLIwSfhNwbdfV13xt0G0JHYjPDAfBgNVHSMEGDAWgBShbYRs ooCFBXx8dXWANMETW5fXgTAJBgNVHRMEAjAAMA4GA1UdDwEB/wQEAwID6DARBglghkgBhvhCAQEE BAMCBLAwHQYDVR0lBBYwFAYIKwYBBQUHAwQGCCsGAQUFBwMCMEoGA1UdHwRDMEEwP6A9oDuGOWh0 dHBzOi8vcGtpLm5ldGFzcS5jb20vYXV0aC9jZXJ0aWZpY2F0ZXJldm9jYXRpb25saXN0LmNybDAR BgNVHSAECjAIMAYGBFUdIAAwKwYDVR0RBCQwIoEgYWxleGFuZHJlLm1hcnRpbnNAc3Rvcm1zaGll bGQuZXUwDQYJKoZIhvcNAQELBQADggEBALT9NWiAaE6nDev34vShhsyb9lWBOQfCnAMyKwtFy/cU uIoHsxyOanIIQHz0ZtB76GCHDo7RStMyp6RYIefIsxABLhSr4hHapJka9g/X/nxexyr0xyT3IpYQ dmyMSHRT18Z/ZaBlQdyfnS2PYkPHJAHl4iqB4SnQlh3rwFdKTJMgCz413cDxQHytgRPGTiXOhyV7 aS3ANJFha6ZHA8HU9sTslY8ZXSUu94iD3t2kcF3gBb432UKALwryKqnrwzFX68pFpqO5QAjEHaF6 6p1agMb2b3HlQGZrME5wSO6rsZJPYvJEyvrwHxCxjSTkOdPw6GriWGTMrVMU0fVrfptMS1gxggIT MIICDwIBATBSMEkxCzAJBgNVBAYTAkZSMRQwEgYDVQQKDAtTVE9STVNISUVMRDEkMCIGA1UEAwwb U3Rvcm1zaGllbGQgVXNlcnMgQXV0aG9yaXR5AgUAhSjLuzANBglghkgBZQMEAgEFAKCBkzAYBgkq hkiG9w0BCQMxCwYJKoZIhvcNAQcBMBwGCSqGSIb3DQEJBTEPFw0xNzAzMTAxNTIzMDJaMCgGCSqG SIb3DQEJDzEbMBkwCwYJYIZIAWUDBAECMAoGCCqGSIb3DQMHMC8GCSqGSIb3DQEJBDEiBCBI1rRJ RzFr0DvQcGiONHPj9reKtdeJSQtGka0UBfCJ0DANBgkqhkiG9w0BAQEFAASCAQCElRTr/3pPGaqu 9oW3oblA99ZMT065PS3ZB8FuTgK/oQ5/StTxHuy9r+L4s285q/qnO/UXzUdINf6WaiHiU4eN+yg6 K8ap7/I/TLD+khemOb8hKENT5rgi/zeAB6jyQ8a2TAwfPa5+PrZb7KIvxvZnpe/YtIapyE8yCW2N GxdDAhyi9hHjmhPVjsa5WPxuZ4rWWoYSwO+TH8SW6z7DGoEBaeoAYMDaeHaIaYMJnzlpMPyRsVje u+R00OtkpgABdyUEtL8hm5Y8Z1zwGmKx9naX2Wdnl+u9ydk3WTlBJd9i3ZCo3E/J9DAAz8Ca08QQ sGWFFF5/HYoHdASqEuUXjTkvAAAAAAAA --nextPart1654324.CXniCo5d1m--
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