Date: Fri, 17 Nov 2006 13:17:14 -0500 From: John Baldwin <jhb@freebsd.org> To: freebsd-current@freebsd.org Cc: Mark Atkinson <atkin901@yahoo.com> Subject: Re: cvs commit: src/sys/dev/bce if_bce.c src/sys/dev/em if_em.c if_em.h src/sys/dev/mpt mpt.h mpt_pci.c Message-ID: <200611171317.14909.jhb@freebsd.org> In-Reply-To: <ejkr4f$s0f$1@sea.gmane.org> References: <200611152004.kAFK4vfe058983@repoman.freebsd.org> <ejkr4f$s0f$1@sea.gmane.org>
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On Friday 17 November 2006 12:22, Mark Atkinson wrote: > (moving to current to avoid dirtying src further) > > John Baldwin wrote: > > jhb 2006-11-15 20:04:57 UTC > > > > FreeBSD src repository > > > > Modified files: > > sys/dev/bce if_bce.c > > sys/dev/em if_em.c if_em.h > > sys/dev/mpt mpt.h mpt_pci.c > > Log: > > Add MSI support to em(4), bce(4), and mpt(4). For now, we only support > > devices that support a maximum of 1 message, and we use that 1 message > > instead of the INTx rid 0 IRQ with the same interrupt handler, etc. > > > > Revision Changes Path > > 1.19 +11 -3 src/sys/dev/bce/if_bce.c > > 1.164 +11 -2 src/sys/dev/em/if_em.c > > 1.56 +1 -0 src/sys/dev/em/if_em.h > > 1.31 +1 -0 src/sys/dev/mpt/mpt.h > > 1.39 +14 -1 src/sys/dev/mpt/mpt_pci.c > > _______________________________________________ > > cvs-src@freebsd.org mailing list > > http://lists.freebsd.org/mailman/listinfo/cvs-src > > To unsubscribe, send any mail to "cvs-src-unsubscribe@freebsd.org" > > This is great, I don't know if you plan on adding MSI support to all network > drivers that could support it, but here's the output from the Tyan S2895 > (k8WE) for the nve0 and nve1 devices, which report supporting 2 messages. > > pcib0: matched entry for 0.10.INTA (src \\_SB_.PCI0.LMAC:0) > pci_link8: Picked IRQ 21 with weight 1 > pcib0: slot 10 INTA routed to irq 21 via \\_SB_.PCI0.LMAC > found-> vendor=0x10de, dev=0x005d, revid=0xa3 > bus=0, slot=14, func=0 > class=06-04-00, hdrtype=0x01, mfdev=0 > cmdreg=0x0107, statreg=0x0010, cachelnsz=16 (dwords) > lattimer=0x00 (0 ns), mingnt=0x0c (3000 ns), maxlat=0x00 (0 ns) > powerspec 2 supports D0 D3 current D0 > MSI supports 2 messages, 64 bit > > [...] > > pcib6: matched entry for 128.10.INTA (src \\_SB_.PCI1.LMAC:0) > pci_link22: Picked IRQ 52 with weight 0 > ioapic3: Changing polarity for pin 20 to high > pcib6: slot 10 INTA routed to irq 52 via \\_SB_.PCI1.LMAC > found-> vendor=0x10de, dev=0x005d, revid=0xa3 > bus=128, slot=14, func=0 > class=06-04-00, hdrtype=0x01, mfdev=0 > cmdreg=0x0107, statreg=0x0010, cachelnsz=16 (dwords) > lattimer=0x00 (0 ns), mingnt=0x04 (1000 ns), maxlat=0x00 (0 ns) > powerspec 2 supports D0 D3 current D0 > MSI supports 2 messages, 64 bit > > nve0@pci0:10:0: class=0x068000 card=0x289510f1 chip=0x005710de rev=0xa3 > hdr=0x00 > vendor = 'NVIDIA Corporation' > device = 'nForce4 Ethernet Controller' > class = bridge > > nve1@pci128:10:0: class=0x068000 card=0x289510f1 chip=0x005710de rev=0xa3 > hdr=0x00 > vendor = 'NVIDIA Corporation' > device = 'nForce4 Ethernet Controller' > class = bridge For devices that support more than 1 message you really need docs to figure out what conditions the different messages are tied to (and if it will work if the system only gives it 1 message instead of 2, etc.) -- John Baldwin
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