Date: Fri, 7 Apr 2006 05:02:05 GMT From: John-Mark Gurney <jmg@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 94751 for review Message-ID: <200604070502.k37525Fr079616@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=94751 Change 94751 by jmg@jmg_carbon-60 on 2006/04/07 05:01:44 clean up pci bridge code a bit.. enable 64bit mode by default... make sure we are using 64bit addressing before using the bits.. don't print wierd addresses when it's really not valid... Affected files ... .. //depot/projects/kmacy_sun4v/src/sys/dev/pci/pci_pci.c#4 edit .. //depot/projects/kmacy_sun4v/src/sys/dev/pci/pcireg.h#3 edit .. //depot/projects/kmacy_sun4v/src/sys/dev/pci/pcivar.h#3 edit Differences ... ==== //depot/projects/kmacy_sun4v/src/sys/dev/pci/pci_pci.c#4 (text+ko) ==== @@ -107,6 +107,7 @@ { struct pcib_softc *sc; uint8_t iolow; + uint32_t memlow; sc = device_get_softc(dev); sc->dev = dev; @@ -128,17 +129,17 @@ iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), - pci_read_config(dev, PCIR_IOBASEL_1, 1)); + iolow); } else { - sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); + sc->iobase = PCI_PPBIOBASE(0, iolow); } iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), - pci_read_config(dev, PCIR_IOLIMITL_1, 1)); + iolow); } else { - sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); + sc->iolimit = PCI_PPBIOLIMIT(0, iolow); } } @@ -146,12 +147,24 @@ * Determine current memory decode. */ if (sc->command & PCIM_CMD_MEMEN) { - sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); - sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); - sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4), - pci_read_config(dev, PCIR_PMBASEL_1, 2)); - sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4), - pci_read_config(dev, PCIR_PMLIMITL_1, 2)); + sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, + PCIR_MEMBASE_1, 2)); + sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, + PCIR_MEMLIMIT_1, 2)); + memlow = pci_read_config(dev, PCIR_PMEMBASEL_1, 2); + if ((memlow & PCIM_BRMEM_MASK) == PCIM_BRMEM_64) { + sc->pmembase = PCI_PPBMEMBASE(pci_read_config(dev, PCIR_PMBASEH_1, + 4), memlow); + } else { + sc->pmembase = PCI_PPBMEMBASE(0, memlow); + } + memhigh = pci_read_config(dev, PCIR_PMLIMITL_1, 4); + if ((memlow & PCIM_BRMEM_MASK) == PCIM_BRMEM_64) { + sc->pmemlimit = PCI_PPBMEMBASE(pci_read_config(dev, PCIR_PMLIMITH_1, + 4), memlow); + } else { + sc->pmemlimit = PCI_PPBMEMBASE(0, memlow); + } } /* @@ -216,9 +229,21 @@ if (bootverbose) { device_printf(dev, " secondary bus %d\n", sc->secbus); device_printf(dev, " subordinate bus %d\n", sc->subbus); - device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); - device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit); - device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit); + if (pcib_is_io_open(sc)) + device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, + sc->iolimit); + else + device_printf(dev, " I/O decode disabled.\n"); + if (pcib_is_nonprefetch_open(sc)) + device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, + sc->memlimit); + else + device_printf(dev, " memory decode disabled.\n"); + if (pcib_is_prefetch_open(sc)) + device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, + sc->pmemlimit); + else + device_printf(dev, " prefetched decode disabled.\n"); if (sc->flags & PCIB_SUBTRACTIVE) device_printf(dev, " Subtractively decoded bridge.\n"); } ==== //depot/projects/kmacy_sun4v/src/sys/dev/pci/pcireg.h#3 (text+ko) ==== @@ -164,6 +164,9 @@ #define PCIR_PMLIMITL_1 0x26 #define PCIR_PMBASEH_1 0x28 #define PCIR_PMLIMITH_1 0x2c +#define PCIM_BRMEM_32 0x0 +#define PCIM_BRMEM_64 0x1 +#define PCIM_BRMEM_MASK 0xf #define PCIR_BRIDGECTL_1 0x3e ==== //depot/projects/kmacy_sun4v/src/sys/dev/pci/pcivar.h#3 (text+ko) ==== @@ -45,11 +45,7 @@ /* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ -#ifdef PCI_A64 typedef uint64_t pci_addr_t; /* uint64_t for system with 64bit addresses */ -#else -typedef uint32_t pci_addr_t; /* uint64_t for system with 64bit addresses */ -#endif /* Interesting values for PCI power management */ struct pcicfg_pp { @@ -108,13 +104,8 @@ /* additional type 1 device config header information (PCI to PCI bridge) */ -#ifdef PCI_A64 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) -#else -#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) -#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) -#endif /* PCI_A64 */ #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff)
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