Date: Mon, 28 Jun 1999 21:29:09 -0700 (PDT) From: Matthew Dillon <dillon@apollo.backplane.com> To: Terry Lambert <tlambert@primenet.com> Cc: julian@whistle.com (Julian Elischer), peter@netplex.com.au, alc@cs.rice.edu, tlambert@primenet.com, bakul@torrentnet.com, freebsd-smp@freebsd.org Subject: Re: high-efficiency SMP locks - submission for review Message-ID: <199906290429.VAA26192@apollo.backplane.com> References: <199906290057.RAA07616@usr05.primenet.com>
next in thread | previous in thread | raw e-mail | index | archive | help
:> and in UP those locks that need atomicity would be optimised away. :> :> We WILL need locking in UP when we move to kernel threads, but that :> doesn't require bus atomicity. : :No one is currently bothering with anything but the Intel MESI :coherency model for SMP, anyway, so I don't understand the :relevence of bus coherency to the argument. : :My only point is that the code needs to degrade gracefully (e.g. :without rebuilding your kernel with a magic doohickey flipped on :or off for no obvious reason). : : Terry Lambert : terry@lambert.org I'm pretty sure that we need bus coherency for general RMW instructions such as add, and, or, etc... Any given cpu will not take an interrupt in the middle of an instruction, but in an SMP environment I do not believe those instructions use indivisible cache-coherent bus cycles. Thus the assembly lock prefix is necesary. I am not absolutely sure of that, but I believe that to be the case for Intel. -Matt To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-smp" in the body of the message
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?199906290429.VAA26192>