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Date:      Fri, 1 Feb 2002 22:50:06 +0100
From:      Erik Trulsson <ertr1013@student.uu.se>
To:        =?iso-8859-1?Q?G=E9rard?= Roudier <groudier@free.fr>
Cc:        Jason Evans <jasone@canonware.com>, Kenneth Culver <culverk@yumyumyum.org>, "Cameron, Frank" <Cameron@ctc.com>, Terry Lambert <tlambert2@mindspring.com>, David Malone <dwmalone@maths.tcd.ie>, "'freebsd-current@freebsd.org'" <freebsd-current@FreeBSD.ORG>
Subject:   Re: AMD AGP Bug
Message-ID:  <20020201215006.GA50090@student.uu.se>
In-Reply-To: <20020131211810.B1769-100000@gerard>
References:  <20020131173408.B63502@canonware.com> <20020131211810.B1769-100000@gerard>

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On Thu, Jan 31, 2002 at 09:32:48PM +0100, G=E9rard Roudier wrote:
>=20
>=20
> On Thu, 31 Jan 2002, Jason Evans wrote:
>=20
> > On Wed, Jan 30, 2002 at 11:14:48PM +0100, G=E9rard Roudier wrote:
> > >
> > > Linux can be fixed, but the useless writes of the existing Athlons fr=
om
> > > the very fast cache to the relatively very slow memory cannot. And all
> > > Athlon users may well pay this penalty under any OS...  unless we wan=
t to
> > > disable caching. :)
> >
> > Have you done benchmarks to show that the speculative writes are useless
> > often enough to cause enough memory bus contention that overall perform=
ance
> > is degraded, despite the speedups when the speculative writes are valid?
>=20
> I haven't done any benchmark of this sort, neither intend to do any since
> I haven't time for that. But I wrote in my email that my 2 Athlon systems
> worked fine and fast, just to indicate that for normal use I didn't see
> any performance problem at all.
>=20
> > I
> > suspect that AMD in fact performed such tests; otherwise they wouldn't =
have
> > gone to the trouble of implementing speculative writes.
>=20
> The Athlon rewriting same value to cacheable memory under the knees of
> programmers looks a severe issue to me if it is true. Not only AGP memory
> can be affected. What about SMP, MMIO (if some cacheable mapping exists),
> etc...?

I am not familiar with the acronym MMIO is so I can't comment on that.=20

In general though, having memoryspace used for memory-mapped I/O
devices (including AGP) marked as cacheable is a bad idea unless you
are very careful and know exactly what you are doing.


For SMP it shouldn't be any problem. Multi-CPU systems normally
run some cache-coherence protocol between themselves to make sure that
things like this is not a problem.


>=20
> In my opinion, OSes having some cacheable mapping to AGP memory is not the
> real problem. Just it has revealed the AMD issue.

It might be argued that there should be some cache-coherence protocol
between the CPU and the AGP device.  Not knowing how AGP is specified I
don't know if this interaction between the CPU and AGP is a bug or just
working as specified.  I suspect it is the latter though.



--=20
<Insert your favourite quote here.>
Erik Trulsson
ertr1013@student.uu.se

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