Date: Sat, 15 Nov 1997 16:53:53 +1100 From: Bruce Evans <bde@zeta.org.au> To: bde@zeta.org.au, mouth@ibm.net Cc: hackers@freebsd.org Subject: Re: Status of 650 UART support Message-ID: <199711150553.QAA31140@godzilla.zeta.org.au>
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>Suppose I set all 8 ports to 460,800 bps and saturate them with >inbound data. With the 32-byte FIFO I might set the trigger level to >16, giving 16 bytes of headroom in each UART, or possibly set the >trigger level to 8, giving 24 bytes of headroom. > >Once I start draining the first UART, will I reach the eighth UART >before it's overrun, and if so, how much margin will I have? I'm not >sure how to calculate the time required for the 8-bit bus cycles. 16 character times at 460800 bps is about 348 usec. The worst case is approximately 8 ports saturated with 32 bytes of input, 32 bytes of output and a modem status change. This takes about 2*32 + 1*32 + 5 i/o's per port. Each i/o takes about 1 usec on an 8MHz ISA bus (perhaps 125 nsec more or less). Altogether, it takes about 8*101 = 808. usec. It won't work. OTOH, there will often be less than 32 bytes of input per port (there will normally be >= 16 because the trigger level is 16), and there may be very little input, depending on the application. Altogether, with saturated input and no output it takes at least about 8*37 = 296 usec. This leaves a whole 52 usec for doing real work. It won't work well. Non-saturated cases might work well. Bruce
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