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Date:      Thu, 30 Mar 2000 21:25:35 +0200
From:      Jesper Skriver <jesper@skriver.dk>
To:        Mike Smith <msmith@freebsd.org>
Cc:        freebsd-current@freebsd.org
Subject:   Re: SMP buildworld times / performance tests
Message-ID:  <20000330212535.A49637@skriver.dk>
In-Reply-To: <200003301805.KAA00452@mass.cdrom.com>; from msmith@freebsd.org on Thu, Mar 30, 2000 at 10:05:26AM -0800
References:  <1274.954416252@critter.freebsd.dk> <200003301805.KAA00452@mass.cdrom.com>

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On Thu, Mar 30, 2000 at 10:05:26AM -0800, Mike Smith wrote:
> > >> Just following on from this, one thing that I can see immediately being 
> > >> very important to me at least is a spinlock in the timecounter structure. 
> > >> Calcru and various other things call microtime(), and we're going to want 
> > >> to lock out updates and parallel accesses to the timecounter.  What 
> > >> should we be using for an interrupt-disabling spinlock?
> > >
> > >Nothing.  Accesses to the timecounter struct are already MP safe and fast.
> > >Only the i8254 timecounter hardware currently needs interrupt-disabling,
> > >but it is hopefully never used on SMP machines.
> > 
> > Worse.  It is used by default on SMP machines which don't sport the
> > PIIX timecounter.
> 
> ie. anything using the PIIX3 or older (think 440FX dual P6 systems, etc.)

On the box below, a relative new dual PIII box, with a Intel
motherboard, does it use the i8254 or the PIIX timecounter ?

Copyright (c) 1992-2000 The FreeBSD Project.
Copyright (c) 1982, 1986, 1989, 1991, 1993
        The Regents of the University of California. All rights reserved.
FreeBSD 4.0-STABLE #0: Mon Mar 27 17:02:42 CEST 2000
    root@:/usr/src/sys/compile/REMIE
Timecounter "i8254"  frequency 1193182 Hz
CPU: Pentium III/Pentium III Xeon (496.66-MHz 686-class CPU)
  Origin = "GenuineIntel"  Id = 0x672  Stepping = 2
Features=0x387fbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,PN,MMX,FXSR,XMM>
real memory  = 268369920 (262080K bytes)
config> q
avail memory = 257515520 (251480K bytes)
Programming 24 pins in IOAPIC #0
IOAPIC #0 intpin 2 -> irq 0
FreeBSD/SMP: Multiprocessor motherboard
 cpu0 (BSP): apic id:  1, version: 0x00040011, at 0xfee00000
 cpu1 (AP):  apic id:  0, version: 0x00040011, at 0xfee00000
 io0 (APIC): apic id:  2, version: 0x00170011, at 0xfec00000
Preloaded elf kernel "kernel" at 0xc02c5000.
Preloaded userconfig_script "/boot/kernel.conf" at 0xc02c509c.
Pentium Pro MTRR support enabled
md0: Malloc disk
npx0: <math processor> on motherboard
npx0: INT 16 interface
pcib0: <Intel 82443BX host to PCI bridge (AGP disabled)> on motherboard
pci0: <PCI bus> on pcib0
[snip]
isab0: <Intel 82371AB PCI to ISA bridge> at device 18.0 on pci0
isa0: <ISA bus> on isab0
pci0: <Intel PIIX4 ATA controller> at 18.1
pci0: <Intel 82371AB/EB (PIIX4) USB controller> at 18.2 irq 10
Timecounter "PIIX"  frequency 3579545 Hz


/Jesper

-- 
Jesper Skriver, jesper(at)skriver(dot)dk  -  CCIE #5456
Work:    Network manager @ AS3292 (Tele Danmark DataNetworks)
Private: Geek            @ AS2109 (A much smaller network ;-)

One Unix to rule them all, One Resolver to find them,
One IP to bring them all and in the zone to bind them.


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