Date: Sun, 02 Jan 2005 19:07:11 -0800 From: Sam Leffler <sam@errno.com> To: Nate Lawson <nate@root.org> Cc: freebsd-acpi@freebsd.org Subject: Re: ACPI C3 patch for atheros Message-ID: <41D8B6DF.7040703@errno.com> In-Reply-To: <41D8B4D2.4050700@root.org> References: <200501021735.j02HZWAs017587@sana.init-main.com> <41D8B4D2.4050700@root.org>
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Nate Lawson wrote: > takawata@jp.freebsd.org wrote: > >> Happy Newyear! >> I was pity to be unable to use atheros wlan adaptor on FreeBSD >> with ACPI. >> >> I checked madwifi archive and I found problem much alike with me in Linux >> and the fix. It seems that it can easyly be applyed to FreeBSD, >> so I tried following patch and it works. >> >> How about this? And should it be in PCI framework? >> >> Index: if_ath_pci.c >> =================================================================== >> RCS file: /home/ncvs/src/sys/dev/ath/if_ath_pci.c,v >> retrieving revision 1.10 >> diff -u -r1.10 if_ath_pci.c >> --- if_ath_pci.c 31 Dec 2004 22:41:45 -0000 1.10 >> +++ if_ath_pci.c 2 Jan 2005 17:30:21 -0000 >> @@ -109,6 +109,9 @@ >> bzero(psc, sizeof (*psc)); >> sc->sc_dev = dev; >> + /*Disable RETRY_TIMEOUT */ >> + pci_write_config(dev, 0x41, 0, 1 ); >> + >> cmd = pci_read_config(dev, PCIR_COMMAND, 4); >> cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; >> pci_write_config(dev, PCIR_COMMAND, cmd, 4); >> @@ -248,6 +251,7 @@ >> struct ath_pci_softc *psc = device_get_softc(dev); >> u_int16_t cmd; >> >> + pci_write_config(dev, 0x41, 0, 1 ); >> pci_write_config(dev, PCIR_INTLINE, psc->sc_saved_intline, 1); >> pci_write_config(dev, PCIR_CACHELNSZ, >> psc->sc_saved_cachelinesz, 1); >> pci_write_config(dev, PCIR_LATTIMER, psc->sc_saved_lattimer, 1); > > > Sorry, I don't know enough about the semantics of this config space > variable to comment in much detail. 0x41 should be a PCIR_ #define though. > > It looks like these config writes in ath_pci_attach() should probably be > done in the PCI bus but they may be driver-specific. The saves of > config space in ath_pci_suspend/resume() are definitely suspect since we > save/resume all config space now. See sys/dev/pci/pci.c > > One other comment: you don't need to bzero a softc since it's allocated > with M_ZERO. > Lots of old code here; at the time I cribbed the suspend-resume code I don't believe the pci registers were saved for drivers. Here's the code from which the change originated: > /* >> * Suspend/Resume resets the PCI configuration space, so we have to >> * re-disable the RETRY_TIMEOUT register (0x41) to keep >> * PCI Tx retries from interfering with C3 CPU state >> * >> * Code taken from ipw2100 driver - jg >> */ >> pci_read_config_dword(pdev, 0x40, &val); >> if ((val & 0x0000ff00) != 0) >> pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); I was waiting for a reply from Warner about whether or not this belonged in the driver or if the pci layer should be handling this. Sam
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