Date: Mon, 07 Feb 2011 15:38:10 -0600 From: Mark Tinguely <marktinguely@gmail.com> To: Marcel Moolenaar <xcllnt@mac.com> Cc: freebsd-arm@freebsd.org Subject: Re: Elimination of cpu_l2cache_* functions Message-ID: <4D506642.5000701@gmail.com> In-Reply-To: <4A878FC3-C011-4E40-8B36-71E36B4C4A11@mac.com> References: <857AA8D9-5C41-4D80-A3B5-0D29BE051014@mac.com> <4D5050B3.4070608@gmail.com> <4A878FC3-C011-4E40-8B36-71E36B4C4A11@mac.com>
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On 2/7/2011 2:37 PM, Marcel Moolenaar wrote: > On Feb 7, 2011, at 12:06 PM, Mark Tinguely wrote: > >> On 2/7/2011 12:43 PM, Marcel Moolenaar wrote: >>> All, >>> >>> I've been reviewing the use of the cpu_l2cache_* functions and found >>> that 1) they're missing from cpu_witch() and 2) they are always used >>> in conjunction with either cpu_idcache_* or cpu_dcache_*. >>> >>> Since most CPU variants define them as null ops, isn't it better to >>> incorporate the functionality of cpu_l2cache_* in cpu_idcache_* and >>> cpu_dcache_* and eliminate them altogether? >>> >>> Any objections to me removing cpu_l2cache_* and therefore changing >>> the semantics of cpu_idcache_* and cpu_dcahce_* to apply to all >>> relevant cache levels? >>> >>> Thanks, >> It was pointed out to me that the level two cache operation were removed from the context switch on purpose, for performance reasons. I think this exception is why we still have both a level one and level two cache operation definitions. >> >> I proposed the senerio that the Sheeva cluster IO filesystem corruption problem is related to level two caches not being written back and removed upon context switch. Assuming we want to keep the performance gain by not performing the level two cache operations when we perform a context switch, and since I believe that the Sheeva has PIPT level two caches, I have a proposed fix to pmap_idcache_wdinv_range() that maps the page to a local KVA and doing the appropriate level two cache operation when needed. >> --- >> In ARMv6 and ARMv7, the inner (level one) caches are PIPT, and all these cache operations go away with the exception of the sync area of the busdma routine. > Hi Mark, > > Yes, the L2 cache on the Sheeva is PIPT, and I think it's safe to remove the > the L2 cache operations from the context switch. However, why do we have L2 > cache operations everywhere else when we only need to worry about it for DMA > and when synchronizing the I-cache in that case right? > Yes, dma sync would be the only place we need to do level-two PIPT cache operations. The new busdma routines with a "sync list" could handle this easily. The "sync list" can be made to remember which pages have an active level-lone cache mapping and and which pages did not. Obviously, the dma sync routine will perform the appropriate level-one cache operations on the pages that were marked as having active mappings and the level-two operations would be done in all cases. If I remember correctly, I played with this idea at one time, but threw it away. --Mark. I
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