Date: Sun, 26 Jun 2016 16:22:41 -0700 From: Mark Millard <markmi@dsl-only.net> To: FreeBSD PowerPC ML <freebsd-ppc@freebsd.org> Subject: Re: svn commit: r302214 - head/sys/powerpc/aim [my PowerMac G5 testing delayed] Message-ID: <B2997643-4FB3-43AF-8942-61E6E4DB2ACF@dsl-only.net>
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Quoting: > Author: nwhitehorn > Date: Sun Jun 26 18:43:42 2016 > New Revision: 302214 > URL:=20 > https://svnweb.freebsd.org/changeset/base/302214 >=20 >=20 > Log: > Enter 64-bit mode as early as possible in the 64-bit PowerPC boot = sequence. > Most of the effect of setting MSR[SF] is that the CPU will stop = ignoring > the high 32 bits of registers containing addresses in load/store > instructions. As such, the kernel was setting it only when it began = to > need access to high memory. MSR[SF] also affects the operation of = some > conditional instructions, however, and so setting it at late times = could > subtly break code at very early times. This fixes use of the FDT = mode in > loader, and FDT boot more generally, on 64-bit PowerPC systems. > =20 > Hardware provided by: IBM LTC > Approved by: re (kib) >=20 > Modified: > head/sys/powerpc/aim/aim_machdep.c > head/sys/powerpc/aim/locore64.S Usually I would test a couple of powerpc64 capable PowerMacs (a = so-called "Quad Core" one and a Dual Processor, single core per = processor, one) for if this changes the boot behavior noticeably for = them. But it will likely be a couple of months or more before I again = have access to them. Hopefully others will happen to test such examples = before then. Context note for PowerMacs used under powerpc64 FreeBSD: When I boot a powerpc64 PowerMac with a FreeBSD for powerpc64 I normally = run with a personal PowerMac specific change to allow reliable booting, = even when there is lots of RAM (8G, 12G, or 16G). The change is tied to = the transitions into and out of Apple's OpenFirmware and I observed it = to avoid memory trashing that I had observed otherwise. When I made this change I effectively eliminated just one instruction = from ofw_sprg_prepare(void): I went for the smallest generated-code = change that made the booting reliable on the PowerMac's that I commonly = have access to. The below just eliminates the pair: "mtsprg0 %1\n\t" and "r"(ofmsr[1]),=20 # svnlite diff /usr/src/sys/powerpc/ofw/ofw_machdep.c=20 Index: /usr/src/sys/powerpc/ofw/ofw_machdep.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- /usr/src/sys/powerpc/ofw/ofw_machdep.c (revision 302180) +++ /usr/src/sys/powerpc/ofw/ofw_machdep.c (working copy) @@ -111,6 +111,24 @@ * Assume that interrupt are disabled at this point, or * SPRG1-3 could be trashed */ +#if defined(AIM) && defined(__powerpc64__) +/* HACK: PowerMac G5 specific code to avoid demonstrated hangs in + * the early boot time frame: avoid mtsprg0 use. + * This would need a live test for PowerMac vs. not in order + * to remove HACK status --but without calling into + * OpenFirmware or the problem would be recreated. + */ + if (1) + __asm __volatile("mfsprg0 %0\n\t" + "mtsprg1 %1\n\t" + "mtsprg2 %2\n\t" + "mtsprg3 %3\n\t" + : "=3D&r"(ofw_sprg0_save) + : "r"(ofmsr[2]), + "r"(ofmsr[3]), + "r"(ofmsr[4])); + else +#endif __asm __volatile("mfsprg0 %0\n\t" "mtsprg0 %1\n\t" "mtsprg1 %2\n\t" I did not change the mfsprg0 nor did I change ofw_sprg_restore(void): = the booting was reliable without any change for those. [I do have access to my sources even though I do not have access to the = PowerMacs for a while.] =3D=3D=3D Mark Millard markmi at dsl-only.net
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