Date: Fri, 5 Apr 2013 09:57:21 -0700 From: Adrian Chadd <adrian@freebsd.org> To: Patrick Kelsey <kelsey@ieee.org> Cc: Dmytro <dioptimizer@gmail.com>, freebsd-mips@freebsd.org Subject: Re: [PATCH] MMC/SD SPI-mode driver Message-ID: <CAJ-Vmo=nQMuuJAW786egjuXCf0LGOd9g%2BCEEKdOJjPLRQFpKUg@mail.gmail.com> In-Reply-To: <CAD44qMURrssyXUz-%2Btd226chPA_MbKJ29ZApozbT2cEYbQwSqw@mail.gmail.com> References: <CAK1zEjs=hC%2BpAYBgGq4t7%2BA_JPLaH6rhvEjD%2B1RNk1Ziu8E-4g@mail.gmail.com> <CAD44qMWpz-sjNKwRH6K=xicFXYutfk7R%2BN%2B%2Bo7cbgTg7rcQbkA@mail.gmail.com> <CAK1zEjuVZU4A59q5GxLcKTnFF9mcrbVmJ=w268uSJ=3sxVf1PA@mail.gmail.com> <CAD44qMURrssyXUz-%2Btd226chPA_MbKJ29ZApozbT2cEYbQwSqw@mail.gmail.com>
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On 5 April 2013 07:57, Patrick Kelsey <kelsey@ieee.org> wrote: > My understanding is that in the AR71xx (and possibly other related > Atheros SoCs), the boot flash can be read through memory mapped access > to a region starting at the reset address, as this is how booting from > a serial flash is accomplished. In that scenario, the SPI controller Yes. > will be translating each read access into an SPI bus transaction that > will produce the desired data from the flash. Since the hardware is > performing the SPI signalling, you wouldn't have the CPU overhead of > bitbanging each SPI bit out. Performance would still be limited by > the value set in the SPI clock divider register (which controls the > bit times on the wire) and the speed of the clock that runs the SPI > unit itself. Yes. The problem here is that we're clocking out 8 bits via bit banging, then we read the 8 bits from the Read register. So luckily we don't have to bitbang the reads and writes, but still. The SPI bus code looks pretty simplistic. There's no DELAY() entries in the SPI code either. The only thing we haven't changed is the SPI clock. Now, what Ray at zrouter did was to experiment with turning SPI _flash_ reads into remap-and-memcpy. Look at ath79_spi_do_read_flash_data(). It's a cute hack to improve read performance, but you _absolutely need to know_ that it's a flash chip and that the bus is locked for the duration of the read. You need the SPI bus locked so you don't have someone come along during a transfer loop and try to fiddle with the SPI registers. The other thing that has shown up is that they're doing some transfers in more than 8 bits at a time? That may also help. Thanks, Adrian
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