Date: Tue, 10 Jan 2012 13:52:49 -0800 From: Adrian Chadd <adrian@freebsd.org> To: Luigi Rizzo <rizzo@iet.unipi.it> Cc: FreeBSD current <freebsd-current@freebsd.org> Subject: Re: memory barriers in bus_dmamap_sync() ? Message-ID: <CAJ-VmomdQ5ZWBf_h1xJhppO8WsinvK7RJiDSgDrYKpo%2BJ8eGYQ@mail.gmail.com> In-Reply-To: <20120110213719.GA92799@onelab2.iet.unipi.it> References: <20120110213719.GA92799@onelab2.iet.unipi.it>
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On 10 January 2012 13:37, Luigi Rizzo <rizzo@iet.unipi.it> wrote: > I was glancing through manpages and implementations of bus_dma(9) > and i am a bit unclear on what this API (in particular, bus_dmamap_sync() ) > does in terms of memory barriers. > > I see that the x86/amd64 and ia64 code only does the bounce buffers. > The mips seems to do some coherency-related calls. > > How do we guarantee, say, that a recently built packet is > to memory before issuing the tx command to the NIC ? The drivers should be good examples of doing the right thing. You just do pre-map and post-map calls as appropriate. Some devices don't bother with this on register accesses and this is a bug. (eg, ath/ath_hal.) Others (eg iwn) do explicit flushes where needed. Adrian
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