Date: Sat, 2 Jan 2016 20:23:26 -0600 From: Jason Browning <jbrowning@uh.edu> To: freebsd-mips@freebsd.org Subject: [RT5350] Boot from flash --> TLB miss (2) Message-ID: <CAK-cGiW%2BiXe%2BON5sryG_ex=1O5-9TWT-e0P0ErRQwd0_=YZRog@mail.gmail.com>
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Hi! I have an RT5350-based board called a =E2=80=98VoCore=E2=80=99 http://vocore.io It=E2=80=99s small - 32M RAM, 16M SPI flash, WiFi, and GPIOs aplenty. I have a software-dev background and am new to embedded-dev, but the FreeBSD documentation and searching this list have brought me a long way. I am now at my limit. I=E2=80=99ve built kernels for (release)RT305X and (current)RT5350, and both work as expected when uploaded as an ELF to RAM and kicked-off with U-Boot=E2=80=99s =E2=80=98go=E2=80=99 command. They both f= ail with the following output when booted from on-board SPI flash: Booting image at bc050000 . Image Name: Created: 2016-01-01 7:14:33 UTC Image Type: MIPS NetBSD Kernel Image (gzip compressed) Data Size: 1580815 Bytes =3D 1.5 MB Load Address: 80000000 Entry Point: 80000100 Load Kernel: ......................... Verifying Checksum ... OK Uncompressing Kernel Image ... OK U-Boot args (from 0 args): None Environment: memsize=3D32 initrd_start=3D0x00000000 initrd_size=3D0x0 flash_start=3D0x00000000 flash_size=3D0x400000 entry: mips_init() Cache info: picache_stride =3D 4096 picache_loopcount =3D 8 pdcache_stride =3D 4096 pdcache_loopcount =3D 4 cpu0: MIPS Technologies processor v76.150 MMU: Standard TLB, 32 entries (4K 16K 64K 256K 1M 16M 64M 256M pg sizes) L1 i-cache: 4 ways of 256 sets, 32 bytes per line L1 d-cache: 4 ways of 128 sets, 32 bytes per line L2 cache: disabled Config1=3D0xbea3319e<PerfCount,WatchRegs,MIPS16,EJTAG> Config2=3D0x80000000 Config3=3D0x420 Physical memory chunk(s): 0x3e0000 - 0x1ffffff, 29491200 bytes (7200 pages) Maxmem is 0x2000000 GDB: debug ports: uart GDB: current port: uart KDB: debugger backends: ddb gdb KDB: current backend: ddb [ thread pid 0 tid 0 ] Stopped at 0x801f43b4 db> bt Tracing pid 0 tid 0 td 0x803646c0 8027896c+30 (?,?,?,?) ra 1880364268 sp 0 sz 0 8000f1b0+114 (0,?,ffffffff,?) ra 2080364280 sp 1 sz 1 8000e4f4+388 (?,?,?,?) ra a8803642a0 sp 0 sz 0 8000e990+70 (?,?,?,?) ra 1880364348 sp 0 sz 0 800110c8+f4 (?,?,?,?) ra 1a880364360 sp 0 sz 0 800f4590+110 (?,?,?,?) ra 3080364508 sp 0 sz 0 trap+d28 (?,?,?,?) ra c080364538 sp 0 sz 0 MipsKernGenException+134 (803f1e98,80355f1c,aba9500,0) ra c8803645f8 sp 100000001 sz 1 801f432c+88 (?,?,?,?) ra 20803646c0 sp 0 sz 0 pid 0 db> reset Trap cause =3D 2 (TLB miss (load or instr. fetch) - kernel mode) panic: trap Uptime: 1s =3D=3D More info: This board came with U-Boot+OpenWRT installed; per the U-Boot config, the FreeBSD kernels were compiled with makeoption KERNLOADADDR=3D0x80100000 when initiated with =E2=80=98go 80100100=E2=80=99 from RAM, and with makeop= tion KERNLOADADDR=3D0x80000000 when initiated with =E2=80=98bootm bc050000=E2=80=99 from SPI flash. I=E2=80=99m out of my depth here, but I *think* things go wrong from within locore.S ([srcRoot]/sys/mips/mips/locore.S) at ~line:177 where: PTR_L a0, TD_PCB(sp) I say this because the problem-scenario seems to make it out of =E2=80=98platform_start=E2=80=99 ([srcRoot]/sys/mips/rt305x/rt305x_machdep.c), and also seems never to enter =E2=80=98mi_startup=E2=80=99 ([srcRoot]/sys/mips/kern/init_main.c). Additionally, I do not know why the flash_size is reported to be only 4M, it=E2=80=99s 16M - verified. I=E2=80=99ve not delved into the intricacies of U-Boot yet. Am I on the wrong track? I=E2=80=99m at my wit=E2=80=99s end with this pro= blem. Jason
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