Date: Wed, 18 Apr 2007 09:20:08 GMT From: Ariff Abdullah <ariff@FreeBSD.org> To: freebsd-i386@FreeBSD.org Subject: Re: i386/104678: SMP not working on Turion XP Laptop Message-ID: <200704180920.l3I9K8ZU067218@freefall.freebsd.org>
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The following reply was made to PR i386/104678; it has been noted by GNATS.
From: Ariff Abdullah <ariff@FreeBSD.org>
To: Rainer Alves <rainer.alves@gmail.com>
Cc: bug-followup@FreeBSD.org, bde@zeta.org.au, danolson@visi.com,
infofarmer@FreeBSD.org, kpitcher@KeithPitcher.com
Subject: Re: i386/104678: SMP not working on Turion XP Laptop
Date: Wed, 18 Apr 2007 17:11:42 +0800
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On Wed, 18 Apr 2007 04:50:11 GMT
Rainer Alves <rainer.alves@gmail.com> wrote:
>
> I've been using your idle_cpu_* patches for about 6 months and
> experienced some minor gliches (system would panic/hang once in a
> while). Your new patch seems a lot simpler, and is working
> perfectly here so far. Thanks!
>
This one should become the final patch (if nobody complains about it).
More thorough check on processor models/revisions especially for
possible future production. Please backout previous patches first
before applying this one.
--
Ariff Abdullah
FreeBSD
... Recording in stereo is obviously too advanced
and confusing for us idiot ***** users :P ........
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Index: src/sys/amd64/amd64/initcpu.c
===================================================================
RCS file: /home/ncvs/src/sys/amd64/amd64/initcpu.c,v
retrieving revision 1.50
diff -u -r1.50 initcpu.c
--- src/sys/amd64/amd64/initcpu.c 19 Jun 2006 22:59:28 -0000 1.50
+++ src/sys/amd64/amd64/initcpu.c 18 Apr 2007 08:52:10 -0000
@@ -79,4 +79,28 @@
wrmsr(MSR_EFER, msr);
pg_nx = PG_NX;
}
+ if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
+ /*
+ * Detect the present of C1E capability mostly on latest
+ * dual-cores (or future) k8 family. This feature render the
+ * apic timer dead, and we disable it by reading Interrupt
+ * Pending Message register and unset both C1eOnCmpHalt
+ * (bit 28) and SmiOnCmpHalt (bit 27).
+ *
+ * Reference:
+ * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh
+ * Processors"
+ * #32559 revision 3.00
+ */
+ if (((cpu_id & 0x00000f00) == 0x00000f00 &&
+ ((cpu_id & 0x000f0000) >= 0x00040000 ||
+ (cpu_id & 0x0ff00000) > 0x00000000)) ||
+ (cpu_id & 0x00000f00) > 0x00000f00) {
+ msr = rdmsr(0xc0010055) & 0x1fffffffULL;
+ if (msr & 0x18000000) {
+ msr &= ~0x18000000ULL;
+ wrmsr(0xc0010055, msr);
+ }
+ }
+ }
}
Index: src/sys/i386/i386/initcpu.c
===================================================================
RCS file: /home/ncvs/src/sys/i386/i386/initcpu.c,v
retrieving revision 1.56
diff -u -r1.56 initcpu.c
--- src/sys/i386/i386/initcpu.c 6 Apr 2007 18:15:02 -0000 1.56
+++ src/sys/i386/i386/initcpu.c 18 Apr 2007 08:52:10 -0000
@@ -658,6 +658,31 @@
break;
}
} else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
+ /*
+ * Detect the present of C1E capability mostly on
+ * latest dual-cores (or future) k8 family. This
+ * feature render the apic timer dead, and we disable
+ * it by reading Interrupt Pending Message register
+ * and unset both C1eOnCmpHalt (bit 28) and
+ * SmiOnCmpHalt (bit 27).
+ *
+ * Reference:
+ * "BIOS and Kernel Developer's Guide for AMD NPT
+ * Family 0Fh Processors"
+ * #32559 revision 3.00
+ */
+ if (((cpu_id & 0x00000f00) == 0x00000f00 &&
+ ((cpu_id & 0x000f0000) >= 0x00040000 ||
+ (cpu_id & 0x0ff00000) > 0x00000000)) ||
+ (cpu_id & 0x00000f00) > 0x00000f00) {
+ u_int64_t msr;
+
+ msr = rdmsr(0xc0010055) & 0x1fffffffULL;
+ if (msr & 0x18000000) {
+ msr &= ~0x18000000ULL;
+ wrmsr(0xc0010055, msr);
+ }
+ }
#if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK)
/*
* Sometimes the BIOS doesn't enable SSE instructions.
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