Date: Tue, 21 May 1996 09:15:10 +0530 From: A JOSEPH KOSHY <koshy@india.hp.com> To: hackers@freebsd.org Subject: I-/D- cache coherency issues Message-ID: <199605210345.AA215120311@fakir.india.hp.com>
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I'm looking at generating machine code on the fly and executing it later.
Since many of the newer uPs have separate I- and D- caches without
consistency checking between the two, this requires a way to ensure
that the instructions executed from a virtual address range are what were
written out to memory by the code generator.
Most I- cache implementations are simple and don't snoop the bus so the
responsibility for maintaining coherency rests with the OS.
Before the list jumps on me about the horrors of self-modifying code
I'd like to point out that rolling your machine code is useful in:
o Direct threaded interpreters: FORTH comes to mind.
o Reiser raster ops: turns out that this is one of the ways you
get decent performance out of torturous hardware like the IBM
(vanilla) VGA --- you generate m/c code for your graphics operation
special cased for operation desired and then let it rip.
o I would hazard a guess that a native mode compiler for the Java
virtual machine would need similar facilities too.
o Then of course there is the amusement value :-).
The magic incantation for correctly executing freshly generated code varies
from a simple "jmp $+2" on a '386 to more arcane calls to PALcode or equivalent
on the newer riscs. I.e. its pretty much processor architecture and memory
architecture dependent.
So my questions are:
(a) Do we have a means in userland of ensuring that a particular range of
virtual addresses is flushed from the I- or D- cache? Something that
would work across {Free,Net,*}BSD hopefully?
(b) Is there a non-m/c specific way this can be done from within the kernel?
I.e. are the suitable kernel VM primitives that one could invoke?
Thanks,
Koshy
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