Skip site navigation (1)Skip section navigation (2)
Date:      Wed, 16 Jan 2002 16:12:51 +1100
From:      Peter Jeremy <peter.jeremy@alcatel.com.au>
To:        John Baldwin <jhb@FreeBSD.org>
Cc:        arch@FreeBSD.org, Thomas Hurst <tom.hurst@clara.net>, "James E. Housley" <jeh@FreeBSD.org>, Bosko Milekic <bmilekic@technokratis.com>, Michal Mertl <mime@traveller.cz>, Terry Lambert <tlambert2@mindspring.com>
Subject:   Re: 64 bit counters again
Message-ID:  <20020116161251.E72285@gsmx07.alcatel.com.au>
In-Reply-To: <XFMail.020115172137.jhb@FreeBSD.org>; from jhb@FreeBSD.org on Tue, Jan 15, 2002 at 05:21:37PM -0800
References:  <20020116120611.A72285@gsmx07.alcatel.com.au> <XFMail.020115172137.jhb@FreeBSD.org>

next in thread | previous in thread | raw e-mail | index | archive | help
On 2002-Jan-15 17:21:37 -0800, John Baldwin <jhb@FreeBSD.org> wrote:
>
>On 16-Jan-02 Peter Jeremy wrote:
>> For the read case, the reader uses something like:
>> 
>> loop: movl    4(mem),%edx
>>       movl    (mem),%eax
>>       cmpl    4(mem),%edx
>>       jnz     loop
>> 
>> If an interrupt updates the MSW then you take another pass around the
>> loop, otherwise you always read the correct value.
>> 
>> For the SMP case, you either need to use locks or you need to use
>> per-CPU counters.  (And the per-CPU counters can be read by another
>> CPU using the above trick).

My parenthetical comment also neglects the effect of per-CPU caches :-(.

>Well, SMP on Pentium's maybe, but not on Alpha, sparc64, or ia64, all of which
>support OOE and looser memory models than x86,

Good point.  The multi-precision counters part is probably only
relevant to IA32 (at least until we need 128-bit counters), but
combining per-CPU counters will be needed in all SMP cases.

I think I'll retract my suggestion that it's possible to read the
counters on any CPU without locking :-).

Locking per-CPU counters defeats most of the justification for having
per-CPU counters in the first place.  (There is still some advantage -
the counters hopefully stay in the local CPU cache instead of
continually jumping between caches).

How about the following:  Have a per-CPU thread to read the per-CPU
counters and update them into common counters.  This could be done either
by having the counter read operation schedule a read on each CPU and
then returning the total, or having a "counter update" thread that runs
in each CPU every (say) second [with a degree of time skew] and
does locked updates into a common central counter.

Peter

To Unsubscribe: send mail to majordomo@FreeBSD.org
with "unsubscribe freebsd-arch" in the body of the message




Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?20020116161251.E72285>