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Date:      Sun, 21 Mar 1999 20:58:21 +0100
From:      Stefan Esser <se@mi.uni-koeln.de>
To:        David Dawes <dawes@rf900.physics.usyd.edu.au>
Cc:        hackers@freebsd.org, Stefan Esser <se@freebsd.org>
Subject:   Re: !! Emergency !! Help FreeBSD 3.0 with IBM Netfinity 5000
Message-ID:  <19990321205821.B557@dialup124.mi.uni-koeln.de>
In-Reply-To: <19990321132356.M11159@rf900.physics.usyd.edu.au>; from David Dawes on Sun, Mar 21, 1999 at 01:23:56PM %2B1100
References:  <4825673A.00577C58.00@tw.ibm.com> <19990321132356.M11159@rf900.physics.usyd.edu.au>

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On 1999-03-21 13:23 +1100, David Dawes <dawes@rf900.physics.usyd.edu.au> wrote:
> >Probing for devices on PCI bus 0:
> >chip0: <Host to PCI bridge (vendor=1166 device=0007)> rev 0x04 on pci0.0.0
> >chip1: <Host to PCI bridge (vendor=1166 device=0005)> rev 0x02 on pci0.0.1
> 
> I guess the problem is multiple host-PCI bridges.  This is something we
> need to deal with at XFree86 too.  Is it correct that there is no
> generic way of handling these?

While PCI to PCI bridges are well defined, there is no standard for 
the position of the secondary bus /subordinate bus registers for 
host to PCI bridges that connect to multiple PCI buses. The standard
asks for one bus with busno=0, where all the other buses are connected
to through PCI to PCI bridges. But that is not what (good) systems with 
many PCI slots have, since each level of PCI to PCI bridges adds latency.

Now there is the problem, that the information about the bus range behind
each of the CPU to PCI bridges is encoded in the device private range of
configuration space, and differently in each device. (If only one CPU to
PCI bridge exists, then buses 0 to 255 are reached through that bridge,
and there is no need to specify that range. But even the Intel Saturn 
chip set back in 1994 had secondary/subordinate bus register in order to
support multiple host bridges. Too bad these registers have not been 
declared mandatory for host bridges, and are hardwired to appropriate
values (secondary bus=1, subordinate bus=255) in chip sets that do not
support multiple directly attached busese ...

Regards, STefan


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