Date: Mon, 5 Nov 2012 00:04:24 GMT From: Robert Watson <rwatson@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 219579 for review Message-ID: <201211050004.qA504OjX066005@skunkworks.freebsd.org>
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http://p4web.freebsd.org/@@219579?ac=10 Change 219579 by rwatson@rwatson_svr_ctsrd_mipsbuild on 2012/11/05 00:03:48 Add macros for CHERI byte/half-word/word/double-word store routines. It looks like the immediate offset might not be supported as yet by the assembler, so omit that from use for now. Affected files ... .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#10 edit Differences ... ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#10 (text+ko) ==== @@ -161,6 +161,30 @@ } while (0) /* + * Data stores; while these don't muck with c0, they do require memory + * clobbers. + */ +#define CHERI_CSB(rs, rt, offset, cb) do { \ + __asm__ __volatile__ ("csb %0, %1($c%2)" : : \ + "r" (rs), "r" (rt), "i" (cb) : "memory"); \ +} while (0) + +#define CHERI_CSH(rs, rt, offset, cb) do { \ + __asm__ __volatile__ ("csh %0, %1($c%2)" : : \ + "r" (rs), "r" (rt), "i" (cb) : "memory"); \ +} while (0) + +#define CHERI_CSW(rs, rt, offset, cb) do { \ + __asm__ __volatile__ ("csw %0, %1($c%2)" : : \ + "r" (rs), "r" (rt), "i" (cb) : "memory"); \ +} while (0) + +#define CHERI_CSD(rs, rt, offset, cb) do { \ + __asm__ __volatile__ ("csd %0, %1($c%2)" : : \ + "r" (rs), "r" (rt), "i" (cb) : "memory"); \ +} while (0) + +/* * Routines that modify or replace values in capability registers, and that if * if used on C0, require the compiler to write registers back to memory, and * reload afterwards, since we may effectively be changing the compiler-
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