Date: Wed, 27 Jun 2018 19:14:32 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r335722 - in vendor/clang/dist-release_60: docs include/clang/Basic include/clang/Driver lib/AST lib/Basic lib/Basic/Targets lib/CodeGen lib/Driver lib/Driver/ToolChains lib/Driver/Tool... Message-ID: <201806271914.w5RJEWPJ042921@repo.freebsd.org>
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Author: dim Date: Wed Jun 27 19:14:32 2018 New Revision: 335722 URL: https://svnweb.freebsd.org/changeset/base/335722 Log: Vendor import of clang 6.0.1 release r335540: https://llvm.org/svn/llvm-project/cfe/tags/RELEASE_601/final@335540 Added: vendor/clang/dist-release_60/test/CodeGen/ms_struct-long-double.c (contents, props changed) vendor/clang/dist-release_60/test/Driver/Inputs/empty.cfg vendor/clang/dist-release_60/test/Driver/config-file4.c (contents, props changed) vendor/clang/dist-release_60/test/Driver/mips-indirect-branch.c (contents, props changed) vendor/clang/dist-release_60/test/Index/Inputs/reparse-issue.h (contents, props changed) vendor/clang/dist-release_60/test/Index/Inputs/reparse-issue.h-0 vendor/clang/dist-release_60/test/Index/Inputs/reparse-issue.h-1 vendor/clang/dist-release_60/test/Index/reparsed-live-issue.cpp (contents, props changed) Modified: vendor/clang/dist-release_60/docs/UsersManual.rst vendor/clang/dist-release_60/include/clang/Basic/DiagnosticDriverKinds.td vendor/clang/dist-release_60/include/clang/Basic/DiagnosticSemaKinds.td vendor/clang/dist-release_60/include/clang/Driver/CLCompatOptions.td vendor/clang/dist-release_60/include/clang/Driver/Options.td vendor/clang/dist-release_60/lib/AST/ExprConstant.cpp vendor/clang/dist-release_60/lib/AST/RecordLayoutBuilder.cpp vendor/clang/dist-release_60/lib/Basic/Targets/AArch64.cpp vendor/clang/dist-release_60/lib/Basic/Targets/Mips.h vendor/clang/dist-release_60/lib/Basic/Targets/X86.cpp vendor/clang/dist-release_60/lib/Basic/Targets/X86.h vendor/clang/dist-release_60/lib/Basic/Version.cpp vendor/clang/dist-release_60/lib/CodeGen/TargetInfo.cpp vendor/clang/dist-release_60/lib/Driver/Driver.cpp vendor/clang/dist-release_60/lib/Driver/ToolChains/Arch/Mips.cpp vendor/clang/dist-release_60/lib/Driver/ToolChains/Arch/Mips.h vendor/clang/dist-release_60/lib/Driver/ToolChains/Clang.cpp vendor/clang/dist-release_60/lib/Driver/ToolChains/CrossWindows.cpp vendor/clang/dist-release_60/lib/Driver/ToolChains/MinGW.cpp vendor/clang/dist-release_60/lib/Frontend/ASTUnit.cpp vendor/clang/dist-release_60/lib/Frontend/CompilerInvocation.cpp vendor/clang/dist-release_60/lib/Headers/avx512vlbitalgintrin.h vendor/clang/dist-release_60/lib/Headers/avx512vlvbmi2intrin.h vendor/clang/dist-release_60/lib/Headers/avx512vlvnniintrin.h vendor/clang/dist-release_60/lib/Sema/SemaDecl.cpp vendor/clang/dist-release_60/test/CodeGen/aarch64-inline-asm.c vendor/clang/dist-release_60/test/CodeGen/attr-target-x86.c vendor/clang/dist-release_60/test/CodeGen/avx512vlbitalg-builtins.c vendor/clang/dist-release_60/test/CodeGen/avx512vlvbmi2-builtins.c vendor/clang/dist-release_60/test/CodeGen/avx512vlvnni-builtins.c vendor/clang/dist-release_60/test/CodeGen/decl.c vendor/clang/dist-release_60/test/CodeGen/function-attributes.c vendor/clang/dist-release_60/test/CodeGen/mingw-long-double.c vendor/clang/dist-release_60/test/CodeGenCXX/const-init-cxx11.cpp vendor/clang/dist-release_60/test/CodeGenCXX/cxx0x-initializer-references.cpp vendor/clang/dist-release_60/test/CodeGenCXX/cxx0x-initializer-stdinitializerlist.cpp vendor/clang/dist-release_60/test/CodeGenObjCXX/arc-cxx11-init-list.mm vendor/clang/dist-release_60/test/Driver/clang_f_opts.c vendor/clang/dist-release_60/test/Driver/mingw-libgcc.c vendor/clang/dist-release_60/test/Driver/mips-features.c vendor/clang/dist-release_60/test/Driver/windows-cross.c vendor/clang/dist-release_60/test/SemaCXX/constant-expression-cxx11.cpp vendor/clang/dist-release_60/test/SemaCXX/warn-missing-variable-declarations.cpp vendor/clang/dist-release_60/tools/driver/driver.cpp Modified: vendor/clang/dist-release_60/docs/UsersManual.rst ============================================================================== --- vendor/clang/dist-release_60/docs/UsersManual.rst Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/docs/UsersManual.rst Wed Jun 27 19:14:32 2018 (r335722) @@ -2741,7 +2741,7 @@ Execute ``clang-cl /?`` to see a list of supported opt /Gv Set __vectorcall as a default calling convention /Gw- Don't put each data item in its own section /Gw Put each data item in its own section - /GX- Enable exception handling + /GX- Disable exception handling /GX Enable exception handling /Gy- Don't put each function in its own section /Gy Put each function in its own section Modified: vendor/clang/dist-release_60/include/clang/Basic/DiagnosticDriverKinds.td ============================================================================== --- vendor/clang/dist-release_60/include/clang/Basic/DiagnosticDriverKinds.td Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/include/clang/Basic/DiagnosticDriverKinds.td Wed Jun 27 19:14:32 2018 (r335722) @@ -326,6 +326,10 @@ def warn_drv_unsupported_abicalls : Warning< "ignoring '-mabicalls' option as it cannot be used with " "non position-independent code and the N64 ABI">, InGroup<OptionIgnored>; +def err_drv_unsupported_indirect_jump_opt : Error< + "'-mindirect-jump=%0' is unsupported with the '%1' architecture">; +def err_drv_unknown_indirect_jump_opt : Error< + "unknown '-mindirect-jump=' option '%0'">; def warn_drv_unable_to_find_directory_expected : Warning< "unable to find %0 directory, expected to be in '%1'">, Modified: vendor/clang/dist-release_60/include/clang/Basic/DiagnosticSemaKinds.td ============================================================================== --- vendor/clang/dist-release_60/include/clang/Basic/DiagnosticSemaKinds.td Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/include/clang/Basic/DiagnosticSemaKinds.td Wed Jun 27 19:14:32 2018 (r335722) @@ -759,6 +759,10 @@ def warn_cxx_ms_struct : Warning<"ms_struct may not produce Microsoft-compatible layouts for classes " "with base classes or virtual functions">, DefaultError, InGroup<IncompatibleMSStruct>; +def warn_npot_ms_struct : + Warning<"ms_struct may not produce Microsoft-compatible layouts with fundamental " + "data types with sizes that aren't a power of two">, + DefaultError, InGroup<IncompatibleMSStruct>; def err_section_conflict : Error<"%0 causes a section type conflict with %1">; def err_no_base_classes : Error<"invalid use of '__super', %0 has no base classes">; def err_invalid_super_scope : Error<"invalid use of '__super', " Modified: vendor/clang/dist-release_60/include/clang/Driver/CLCompatOptions.td ============================================================================== --- vendor/clang/dist-release_60/include/clang/Driver/CLCompatOptions.td Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/include/clang/Driver/CLCompatOptions.td Wed Jun 27 19:14:32 2018 (r335722) @@ -238,7 +238,7 @@ def _SLASH_Fo : CLCompileJoined<"Fo">, def _SLASH_GX : CLFlag<"GX">, HelpText<"Enable exception handling">; def _SLASH_GX_ : CLFlag<"GX-">, - HelpText<"Enable exception handling">; + HelpText<"Disable exception handling">; def _SLASH_imsvc : CLJoinedOrSeparate<"imsvc">, HelpText<"Add directory to system include search path, as if part of %INCLUDE%">, MetaVarName<"<dir>">; Modified: vendor/clang/dist-release_60/include/clang/Driver/Options.td ============================================================================== --- vendor/clang/dist-release_60/include/clang/Driver/Options.td Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/include/clang/Driver/Options.td Wed Jun 27 19:14:32 2018 (r335722) @@ -1100,7 +1100,8 @@ def fthinlto_index_EQ : Joined<["-"], "fthinlto-index= HelpText<"Perform ThinLTO importing using provided function summary index">; def fmacro_backtrace_limit_EQ : Joined<["-"], "fmacro-backtrace-limit=">, Group<f_Group>, Flags<[DriverOption, CoreOption]>; -def fmerge_all_constants : Flag<["-"], "fmerge-all-constants">, Group<f_Group>; +def fmerge_all_constants : Flag<["-"], "fmerge-all-constants">, Group<f_Group>, + Flags<[CC1Option]>, HelpText<"Allow merging of constants">; def fmessage_length_EQ : Joined<["-"], "fmessage-length=">, Group<f_Group>; def fms_extensions : Flag<["-"], "fms-extensions">, Group<f_Group>, Flags<[CC1Option, CoreOption]>, HelpText<"Accept some non-standard constructs supported by the Microsoft compiler">; @@ -1249,7 +1250,7 @@ def fveclib : Joined<["-"], "fveclib=">, Group<f_Group def fno_lax_vector_conversions : Flag<["-"], "fno-lax-vector-conversions">, Group<f_Group>, HelpText<"Disallow implicit conversions between vectors with a different number of elements or different element types">, Flags<[CC1Option]>; def fno_merge_all_constants : Flag<["-"], "fno-merge-all-constants">, Group<f_Group>, - Flags<[CC1Option]>, HelpText<"Disallow merging of constants">; + HelpText<"Disallow merging of constants">; def fno_modules : Flag <["-"], "fno-modules">, Group<f_Group>, Flags<[DriverOption]>; def fno_implicit_module_maps : Flag <["-"], "fno-implicit-module-maps">, Group<f_Group>, @@ -1992,6 +1993,9 @@ def mbranch_likely : Flag<["-"], "mbranch-likely">, Gr IgnoredGCCCompat; def mno_branch_likely : Flag<["-"], "mno-branch-likely">, Group<m_Group>, IgnoredGCCCompat; +def mindirect_jump_EQ : Joined<["-"], "mindirect-jump=">, + Group<m_Group>, + HelpText<"Change indirect jump instructions to inhibit speculation">; def mdsp : Flag<["-"], "mdsp">, Group<m_Group>; def mno_dsp : Flag<["-"], "mno-dsp">, Group<m_Group>; def mdspr2 : Flag<["-"], "mdspr2">, Group<m_Group>; @@ -2559,6 +2563,8 @@ def mrtm : Flag<["-"], "mrtm">, Group<m_x86_Features_G def mno_rtm : Flag<["-"], "mno-rtm">, Group<m_x86_Features_Group>; def mrdseed : Flag<["-"], "mrdseed">, Group<m_x86_Features_Group>; def mno_rdseed : Flag<["-"], "mno-rdseed">, Group<m_x86_Features_Group>; +def msahf : Flag<["-"], "msahf">, Group<m_x86_Features_Group>; +def mno_sahf : Flag<["-"], "mno-sahf">, Group<m_x86_Features_Group>; def msgx : Flag<["-"], "msgx">, Group<m_x86_Features_Group>; def mno_sgx : Flag<["-"], "mno-sgx">, Group<m_x86_Features_Group>; def msha : Flag<["-"], "msha">, Group<m_x86_Features_Group>; Modified: vendor/clang/dist-release_60/lib/AST/ExprConstant.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/AST/ExprConstant.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/AST/ExprConstant.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -61,14 +61,22 @@ namespace { static QualType getType(APValue::LValueBase B) { if (!B) return QualType(); - if (const ValueDecl *D = B.dyn_cast<const ValueDecl*>()) + if (const ValueDecl *D = B.dyn_cast<const ValueDecl*>()) { // FIXME: It's unclear where we're supposed to take the type from, and - // this actually matters for arrays of unknown bound. Using the type of - // the most recent declaration isn't clearly correct in general. Eg: + // this actually matters for arrays of unknown bound. Eg: // // extern int arr[]; void f() { extern int arr[3]; }; // constexpr int *p = &arr[1]; // valid? - return cast<ValueDecl>(D->getMostRecentDecl())->getType(); + // + // For now, we take the array bound from the most recent declaration. + for (auto *Redecl = cast<ValueDecl>(D->getMostRecentDecl()); Redecl; + Redecl = cast_or_null<ValueDecl>(Redecl->getPreviousDecl())) { + QualType T = Redecl->getType(); + if (!T->isIncompleteArrayType()) + return T; + } + return D->getType(); + } const Expr *Base = B.get<const Expr*>(); @@ -8535,9 +8543,6 @@ bool IntExprEvaluator::VisitBinaryOperator(const Binar (LHSValue.Base && isZeroSized(RHSValue))) return Error(E); // Pointers with different bases cannot represent the same object. - // (Note that clang defaults to -fmerge-all-constants, which can - // lead to inconsistent results for comparisons involving the address - // of a constant; this generally doesn't matter in practice.) return Success(E->getOpcode() == BO_NE, E); } Modified: vendor/clang/dist-release_60/lib/AST/RecordLayoutBuilder.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/AST/RecordLayoutBuilder.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/AST/RecordLayoutBuilder.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -1751,7 +1751,34 @@ void ItaniumRecordLayoutBuilder::LayoutField(const Fie QualType T = Context.getBaseElementType(D->getType()); if (const BuiltinType *BTy = T->getAs<BuiltinType>()) { CharUnits TypeSize = Context.getTypeSizeInChars(BTy); - if (TypeSize > FieldAlign) + + if (!llvm::isPowerOf2_64(TypeSize.getQuantity())) { + assert( + !Context.getTargetInfo().getTriple().isWindowsMSVCEnvironment() && + "Non PowerOf2 size in MSVC mode"); + // Base types with sizes that aren't a power of two don't work + // with the layout rules for MS structs. This isn't an issue in + // MSVC itself since there are no such base data types there. + // On e.g. x86_32 mingw and linux, long double is 12 bytes though. + // Any structs involving that data type obviously can't be ABI + // compatible with MSVC regardless of how it is laid out. + + // Since ms_struct can be mass enabled (via a pragma or via the + // -mms-bitfields command line parameter), this can trigger for + // structs that don't actually need MSVC compatibility, so we + // need to be able to sidestep the ms_struct layout for these types. + + // Since the combination of -mms-bitfields together with structs + // like max_align_t (which contains a long double) for mingw is + // quite comon (and GCC handles it silently), just handle it + // silently there. For other targets that have ms_struct enabled + // (most probably via a pragma or attribute), trigger a diagnostic + // that defaults to an error. + if (!Context.getTargetInfo().getTriple().isWindowsGNUEnvironment()) + Diag(D->getLocation(), diag::warn_npot_ms_struct); + } + if (TypeSize > FieldAlign && + llvm::isPowerOf2_64(TypeSize.getQuantity())) FieldAlign = TypeSize; } } Modified: vendor/clang/dist-release_60/lib/Basic/Targets/AArch64.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Basic/Targets/AArch64.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Basic/Targets/AArch64.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -299,7 +299,40 @@ ArrayRef<const char *> AArch64TargetInfo::getGCCRegNam } const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { - {{"w31"}, "wsp"}, {{"x29"}, "fp"}, {{"x30"}, "lr"}, {{"x31"}, "sp"}, + {{"w31"}, "wsp"}, + {{"x31"}, "sp"}, + // GCC rN registers are aliases of xN registers. + {{"r0"}, "x0"}, + {{"r1"}, "x1"}, + {{"r2"}, "x2"}, + {{"r3"}, "x3"}, + {{"r4"}, "x4"}, + {{"r5"}, "x5"}, + {{"r6"}, "x6"}, + {{"r7"}, "x7"}, + {{"r8"}, "x8"}, + {{"r9"}, "x9"}, + {{"r10"}, "x10"}, + {{"r11"}, "x11"}, + {{"r12"}, "x12"}, + {{"r13"}, "x13"}, + {{"r14"}, "x14"}, + {{"r15"}, "x15"}, + {{"r16"}, "x16"}, + {{"r17"}, "x17"}, + {{"r18"}, "x18"}, + {{"r19"}, "x19"}, + {{"r20"}, "x20"}, + {{"r21"}, "x21"}, + {{"r22"}, "x22"}, + {{"r23"}, "x23"}, + {{"r24"}, "x24"}, + {{"r25"}, "x25"}, + {{"r26"}, "x26"}, + {{"r27"}, "x27"}, + {{"r28"}, "x28"}, + {{"r29", "x29"}, "fp"}, + {{"r30", "x30"}, "lr"}, // The S/D/Q and W/X registers overlap, but aren't really aliases; we // don't want to substitute one of these for a different-sized one. }; Modified: vendor/clang/dist-release_60/lib/Basic/Targets/Mips.h ============================================================================== --- vendor/clang/dist-release_60/lib/Basic/Targets/Mips.h Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Basic/Targets/Mips.h Wed Jun 27 19:14:32 2018 (r335722) @@ -54,6 +54,7 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public enum DspRevEnum { NoDSP, DSP1, DSP2 } DspRev; bool HasMSA; bool DisableMadd4; + bool UseIndirectJumpHazard; protected: bool HasFP64; @@ -64,7 +65,8 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public : TargetInfo(Triple), IsMips16(false), IsMicromips(false), IsNan2008(false), IsAbs2008(false), IsSingleFloat(false), IsNoABICalls(false), CanUseBSDABICalls(false), FloatABI(HardFloat), - DspRev(NoDSP), HasMSA(false), DisableMadd4(false), HasFP64(false) { + DspRev(NoDSP), HasMSA(false), DisableMadd4(false), + UseIndirectJumpHazard(false), HasFP64(false) { TheCXXABI.set(TargetCXXABI::GenericMIPS); setABI((getTriple().getArch() == llvm::Triple::mips || @@ -338,6 +340,8 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public IsAbs2008 = false; else if (Feature == "+noabicalls") IsNoABICalls = true; + else if (Feature == "+use-indirect-jump-hazard") + UseIndirectJumpHazard = true; } setDataLayout(); Modified: vendor/clang/dist-release_60/lib/Basic/Targets/X86.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Basic/Targets/X86.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Basic/Targets/X86.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -198,6 +198,7 @@ bool X86TargetInfo::initFeatureMap( LLVM_FALLTHROUGH; case CK_Core2: setFeatureEnabledImpl(Features, "ssse3", true); + setFeatureEnabledImpl(Features, "sahf", true); LLVM_FALLTHROUGH; case CK_Yonah: case CK_Prescott: @@ -239,6 +240,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "ssse3", true); setFeatureEnabledImpl(Features, "fxsr", true); setFeatureEnabledImpl(Features, "cx16", true); + setFeatureEnabledImpl(Features, "sahf", true); break; case CK_KNM: @@ -269,6 +271,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "xsaveopt", true); setFeatureEnabledImpl(Features, "xsave", true); setFeatureEnabledImpl(Features, "movbe", true); + setFeatureEnabledImpl(Features, "sahf", true); break; case CK_K6_2: @@ -282,6 +285,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "sse4a", true); setFeatureEnabledImpl(Features, "lzcnt", true); setFeatureEnabledImpl(Features, "popcnt", true); + setFeatureEnabledImpl(Features, "sahf", true); LLVM_FALLTHROUGH; case CK_K8SSE3: setFeatureEnabledImpl(Features, "sse3", true); @@ -315,6 +319,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "prfchw", true); setFeatureEnabledImpl(Features, "cx16", true); setFeatureEnabledImpl(Features, "fxsr", true); + setFeatureEnabledImpl(Features, "sahf", true); break; case CK_ZNVER1: @@ -338,6 +343,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "prfchw", true); setFeatureEnabledImpl(Features, "rdrnd", true); setFeatureEnabledImpl(Features, "rdseed", true); + setFeatureEnabledImpl(Features, "sahf", true); setFeatureEnabledImpl(Features, "sha", true); setFeatureEnabledImpl(Features, "sse4a", true); setFeatureEnabledImpl(Features, "xsave", true); @@ -372,6 +378,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "cx16", true); setFeatureEnabledImpl(Features, "fxsr", true); setFeatureEnabledImpl(Features, "xsave", true); + setFeatureEnabledImpl(Features, "sahf", true); break; } if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) @@ -768,6 +775,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<s HasRetpoline = true; } else if (Feature == "+retpoline-external-thunk") { HasRetpolineExternalThunk = true; + } else if (Feature == "+sahf") { + HasLAHFSAHF = true; } X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) @@ -1240,6 +1249,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) .Case("rdrnd", true) .Case("rdseed", true) .Case("rtm", true) + .Case("sahf", true) .Case("sgx", true) .Case("sha", true) .Case("shstk", true) @@ -1313,6 +1323,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) cons .Case("retpoline", HasRetpoline) .Case("retpoline-external-thunk", HasRetpolineExternalThunk) .Case("rtm", HasRTM) + .Case("sahf", HasLAHFSAHF) .Case("sgx", HasSGX) .Case("sha", HasSHA) .Case("shstk", HasSHSTK) Modified: vendor/clang/dist-release_60/lib/Basic/Targets/X86.h ============================================================================== --- vendor/clang/dist-release_60/lib/Basic/Targets/X86.h Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Basic/Targets/X86.h Wed Jun 27 19:14:32 2018 (r335722) @@ -98,6 +98,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public T bool HasPREFETCHWT1 = false; bool HasRetpoline = false; bool HasRetpolineExternalThunk = false; + bool HasLAHFSAHF = false; /// \brief Enumeration of all of the X86 CPUs supported by Clang. /// Modified: vendor/clang/dist-release_60/lib/Basic/Version.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Basic/Version.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Basic/Version.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -36,7 +36,7 @@ std::string getClangRepositoryPath() { // If the SVN_REPOSITORY is empty, try to use the SVN keyword. This helps us // pick up a tag in an SVN export, for example. - StringRef SVNRepository("$URL: https://llvm.org/svn/llvm-project/cfe/tags/RELEASE_600/final/lib/Basic/Version.cpp $"); + StringRef SVNRepository("$URL: https://llvm.org/svn/llvm-project/cfe/tags/RELEASE_601/final/lib/Basic/Version.cpp $"); if (URL.empty()) { URL = SVNRepository.slice(SVNRepository.find(':'), SVNRepository.find("/lib/Basic")); Modified: vendor/clang/dist-release_60/lib/CodeGen/TargetInfo.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/CodeGen/TargetInfo.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/CodeGen/TargetInfo.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -1931,13 +1931,8 @@ void X86_32TargetCodeGenInfo::setTargetAttributes( return; if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) { if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) { - // Get the LLVM function. llvm::Function *Fn = cast<llvm::Function>(GV); - - // Now add the 'alignstack' attribute with a value of 16. - llvm::AttrBuilder B; - B.addStackAlignmentAttr(16); - Fn->addAttributes(llvm::AttributeList::FunctionIndex, B); + Fn->addFnAttr("stackrealign"); } if (FD->hasAttr<AnyX86InterruptAttr>()) { llvm::Function *Fn = cast<llvm::Function>(GV); @@ -2292,13 +2287,8 @@ class X86_64TargetCodeGenInfo : public TargetCodeGenIn return; if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) { if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) { - // Get the LLVM function. - auto *Fn = cast<llvm::Function>(GV); - - // Now add the 'alignstack' attribute with a value of 16. - llvm::AttrBuilder B; - B.addStackAlignmentAttr(16); - Fn->addAttributes(llvm::AttributeList::FunctionIndex, B); + llvm::Function *Fn = cast<llvm::Function>(GV); + Fn->addFnAttr("stackrealign"); } if (FD->hasAttr<AnyX86InterruptAttr>()) { llvm::Function *Fn = cast<llvm::Function>(GV); @@ -2429,13 +2419,8 @@ void WinX86_64TargetCodeGenInfo::setTargetAttributes( return; if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) { if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) { - // Get the LLVM function. - auto *Fn = cast<llvm::Function>(GV); - - // Now add the 'alignstack' attribute with a value of 16. - llvm::AttrBuilder B; - B.addStackAlignmentAttr(16); - Fn->addAttributes(llvm::AttributeList::FunctionIndex, B); + llvm::Function *Fn = cast<llvm::Function>(GV); + Fn->addFnAttr("stackrealign"); } if (FD->hasAttr<AnyX86InterruptAttr>()) { llvm::Function *Fn = cast<llvm::Function>(GV); Modified: vendor/clang/dist-release_60/lib/Driver/Driver.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Driver/Driver.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Driver/Driver.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -858,11 +858,14 @@ Compilation *Driver::BuildCompilation(ArrayRef<const c : std::move(*CLOptions)); if (HasConfigFile) for (auto *Opt : *CLOptions) { + if (Opt->getOption().matches(options::OPT_config)) + continue; + unsigned Index = Args.MakeIndex(Opt->getSpelling()); const Arg *BaseArg = &Opt->getBaseArg(); if (BaseArg == Opt) BaseArg = nullptr; Arg *Copy = new llvm::opt::Arg(Opt->getOption(), Opt->getSpelling(), - Args.size(), BaseArg); + Index, BaseArg); Copy->getValues() = Opt->getValues(); if (Opt->isClaimed()) Copy->claim(); Modified: vendor/clang/dist-release_60/lib/Driver/ToolChains/Arch/Mips.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Driver/ToolChains/Arch/Mips.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Driver/ToolChains/Arch/Mips.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -343,6 +343,28 @@ void mips::getMIPSTargetFeatures(const Driver &D, cons AddTargetFeature(Args, Features, options::OPT_mno_madd4, options::OPT_mmadd4, "nomadd4"); AddTargetFeature(Args, Features, options::OPT_mmt, options::OPT_mno_mt, "mt"); + + if (Arg *A = Args.getLastArg(options::OPT_mindirect_jump_EQ)) { + StringRef Val = StringRef(A->getValue()); + if (Val == "hazard") { + Arg *B = + Args.getLastArg(options::OPT_mmicromips, options::OPT_mno_micromips); + Arg *C = Args.getLastArg(options::OPT_mips16, options::OPT_mno_mips16); + + if (B && B->getOption().matches(options::OPT_mmicromips)) + D.Diag(diag::err_drv_unsupported_indirect_jump_opt) + << "hazard" << "micromips"; + else if (C && C->getOption().matches(options::OPT_mips16)) + D.Diag(diag::err_drv_unsupported_indirect_jump_opt) + << "hazard" << "mips16"; + else if (mips::supportsIndirectJumpHazardBarrier(CPUName)) + Features.push_back("+use-indirect-jump-hazard"); + else + D.Diag(diag::err_drv_unsupported_indirect_jump_opt) + << "hazard" << CPUName; + } else + D.Diag(diag::err_drv_unknown_indirect_jump_opt) << Val; + } } mips::IEEE754Standard mips::getIEEE754Standard(StringRef &CPU) { @@ -446,4 +468,21 @@ bool mips::shouldUseFPXX(const ArgList &Args, const ll UseFPXX = false; return UseFPXX; +} + +bool mips::supportsIndirectJumpHazardBarrier(StringRef &CPU) { + // Supporting the hazard barrier method of dealing with indirect + // jumps requires MIPSR2 support. + return llvm::StringSwitch<bool>(CPU) + .Case("mips32r2", true) + .Case("mips32r3", true) + .Case("mips32r5", true) + .Case("mips32r6", true) + .Case("mips64r2", true) + .Case("mips64r3", true) + .Case("mips64r5", true) + .Case("mips64r6", true) + .Case("octeon", true) + .Case("p5600", true) + .Default(false); } Modified: vendor/clang/dist-release_60/lib/Driver/ToolChains/Arch/Mips.h ============================================================================== --- vendor/clang/dist-release_60/lib/Driver/ToolChains/Arch/Mips.h Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Driver/ToolChains/Arch/Mips.h Wed Jun 27 19:14:32 2018 (r335722) @@ -53,6 +53,7 @@ bool isFPXXDefault(const llvm::Triple &Triple, StringR bool shouldUseFPXX(const llvm::opt::ArgList &Args, const llvm::Triple &Triple, StringRef CPUName, StringRef ABIName, mips::FloatABI FloatABI); +bool supportsIndirectJumpHazardBarrier(StringRef &CPU); } // end namespace mips } // end namespace target Modified: vendor/clang/dist-release_60/lib/Driver/ToolChains/Clang.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Driver/ToolChains/Clang.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Driver/ToolChains/Clang.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -3288,9 +3288,9 @@ void Clang::ConstructJob(Compilation &C, const JobActi Args.AddLastArg(CmdArgs, options::OPT_fveclib); - if (!Args.hasFlag(options::OPT_fmerge_all_constants, - options::OPT_fno_merge_all_constants)) - CmdArgs.push_back("-fno-merge-all-constants"); + if (Args.hasFlag(options::OPT_fmerge_all_constants, + options::OPT_fno_merge_all_constants, false)) + CmdArgs.push_back("-fmerge-all-constants"); // LLVM Code Generator Options. Modified: vendor/clang/dist-release_60/lib/Driver/ToolChains/CrossWindows.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Driver/ToolChains/CrossWindows.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Driver/ToolChains/CrossWindows.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -127,7 +127,8 @@ void tools::CrossWindows::Linker::ConstructJob( } CmdArgs.push_back("-shared"); - CmdArgs.push_back("-Bdynamic"); + CmdArgs.push_back(Args.hasArg(options::OPT_static) ? "-Bstatic" + : "-Bdynamic"); CmdArgs.push_back("--enable-auto-image-base"); Modified: vendor/clang/dist-release_60/lib/Driver/ToolChains/MinGW.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Driver/ToolChains/MinGW.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Driver/ToolChains/MinGW.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -141,22 +141,21 @@ void tools::MinGW::Linker::ConstructJob(Compilation &C CmdArgs.push_back("console"); } + if (Args.hasArg(options::OPT_mdll)) + CmdArgs.push_back("--dll"); + else if (Args.hasArg(options::OPT_shared)) + CmdArgs.push_back("--shared"); if (Args.hasArg(options::OPT_static)) CmdArgs.push_back("-Bstatic"); - else { - if (Args.hasArg(options::OPT_mdll)) - CmdArgs.push_back("--dll"); - else if (Args.hasArg(options::OPT_shared)) - CmdArgs.push_back("--shared"); + else CmdArgs.push_back("-Bdynamic"); - if (Args.hasArg(options::OPT_mdll) || Args.hasArg(options::OPT_shared)) { - CmdArgs.push_back("-e"); - if (TC.getArch() == llvm::Triple::x86) - CmdArgs.push_back("_DllMainCRTStartup@12"); - else - CmdArgs.push_back("DllMainCRTStartup"); - CmdArgs.push_back("--enable-auto-image-base"); - } + if (Args.hasArg(options::OPT_mdll) || Args.hasArg(options::OPT_shared)) { + CmdArgs.push_back("-e"); + if (TC.getArch() == llvm::Triple::x86) + CmdArgs.push_back("_DllMainCRTStartup@12"); + else + CmdArgs.push_back("DllMainCRTStartup"); + CmdArgs.push_back("--enable-auto-image-base"); } CmdArgs.push_back("-o"); Modified: vendor/clang/dist-release_60/lib/Frontend/ASTUnit.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Frontend/ASTUnit.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Frontend/ASTUnit.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -1259,6 +1259,7 @@ ASTUnit::getMainBufferWithPrecompiledPreamble( Preamble.reset(); PreambleDiagnostics.clear(); TopLevelDeclsInPreamble.clear(); + PreambleSrcLocCache.clear(); PreambleRebuildCounter = 1; } } Modified: vendor/clang/dist-release_60/lib/Frontend/CompilerInvocation.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Frontend/CompilerInvocation.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Frontend/CompilerInvocation.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -552,7 +552,7 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, Arg Args.hasFlag(OPT_ffine_grained_bitfield_accesses, OPT_fno_fine_grained_bitfield_accesses, false); Opts.DwarfDebugFlags = Args.getLastArgValue(OPT_dwarf_debug_flags); - Opts.MergeAllConstants = !Args.hasArg(OPT_fno_merge_all_constants); + Opts.MergeAllConstants = Args.hasArg(OPT_fmerge_all_constants); Opts.NoCommon = Args.hasArg(OPT_fno_common); Opts.NoImplicitFloat = Args.hasArg(OPT_no_implicit_float); Opts.OptimizeSize = getOptimizationLevelSize(Args); Modified: vendor/clang/dist-release_60/lib/Headers/avx512vlbitalgintrin.h ============================================================================== --- vendor/clang/dist-release_60/lib/Headers/avx512vlbitalgintrin.h Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Headers/avx512vlbitalgintrin.h Wed Jun 27 19:14:32 2018 (r335722) @@ -54,23 +54,23 @@ _mm256_maskz_popcnt_epi16(__mmask16 __U, __m256i __B) } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_popcnt_epi16(__m128i __A) +_mm_popcnt_epi16(__m128i __A) { return (__m128i) __builtin_ia32_vpopcntw_128((__v8hi) __A); } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_mask_popcnt_epi16(__m128i __A, __mmask8 __U, __m128i __B) +_mm_mask_popcnt_epi16(__m128i __A, __mmask8 __U, __m128i __B) { return (__m128i) __builtin_ia32_selectw_128((__mmask8) __U, - (__v8hi) _mm128_popcnt_epi16(__B), + (__v8hi) _mm_popcnt_epi16(__B), (__v8hi) __A); } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_maskz_popcnt_epi16(__mmask8 __U, __m128i __B) +_mm_maskz_popcnt_epi16(__mmask8 __U, __m128i __B) { - return _mm128_mask_popcnt_epi16((__m128i) _mm_setzero_si128(), + return _mm_mask_popcnt_epi16((__m128i) _mm_setzero_si128(), __U, __B); } @@ -98,29 +98,29 @@ _mm256_maskz_popcnt_epi8(__mmask32 __U, __m256i __B) } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_popcnt_epi8(__m128i __A) +_mm_popcnt_epi8(__m128i __A) { return (__m128i) __builtin_ia32_vpopcntb_128((__v16qi) __A); } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_mask_popcnt_epi8(__m128i __A, __mmask16 __U, __m128i __B) +_mm_mask_popcnt_epi8(__m128i __A, __mmask16 __U, __m128i __B) { return (__m128i) __builtin_ia32_selectb_128((__mmask16) __U, - (__v16qi) _mm128_popcnt_epi8(__B), + (__v16qi) _mm_popcnt_epi8(__B), (__v16qi) __A); } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_maskz_popcnt_epi8(__mmask16 __U, __m128i __B) +_mm_maskz_popcnt_epi8(__mmask16 __U, __m128i __B) { - return _mm128_mask_popcnt_epi8((__m128i) _mm_setzero_si128(), + return _mm_mask_popcnt_epi8((__m128i) _mm_setzero_si128(), __U, __B); } static __inline__ __mmask32 __DEFAULT_FN_ATTRS -_mm256_mask_bitshuffle_epi32_mask(__mmask32 __U, __m256i __A, __m256i __B) +_mm256_mask_bitshuffle_epi64_mask(__mmask32 __U, __m256i __A, __m256i __B) { return (__mmask32) __builtin_ia32_vpshufbitqmb256_mask((__v32qi) __A, (__v32qi) __B, @@ -128,15 +128,15 @@ _mm256_mask_bitshuffle_epi32_mask(__mmask32 __U, __m25 } static __inline__ __mmask32 __DEFAULT_FN_ATTRS -_mm256_bitshuffle_epi32_mask(__m256i __A, __m256i __B) +_mm256_bitshuffle_epi64_mask(__m256i __A, __m256i __B) { - return _mm256_mask_bitshuffle_epi32_mask((__mmask32) -1, + return _mm256_mask_bitshuffle_epi64_mask((__mmask32) -1, __A, __B); } static __inline__ __mmask16 __DEFAULT_FN_ATTRS -_mm128_mask_bitshuffle_epi16_mask(__mmask16 __U, __m128i __A, __m128i __B) +_mm_mask_bitshuffle_epi64_mask(__mmask16 __U, __m128i __A, __m128i __B) { return (__mmask16) __builtin_ia32_vpshufbitqmb128_mask((__v16qi) __A, (__v16qi) __B, @@ -144,9 +144,9 @@ _mm128_mask_bitshuffle_epi16_mask(__mmask16 __U, __m12 } static __inline__ __mmask16 __DEFAULT_FN_ATTRS -_mm128_bitshuffle_epi16_mask(__m128i __A, __m128i __B) +_mm_bitshuffle_epi64_mask(__m128i __A, __m128i __B) { - return _mm128_mask_bitshuffle_epi16_mask((__mmask16) -1, + return _mm_mask_bitshuffle_epi64_mask((__mmask16) -1, __A, __B); } Modified: vendor/clang/dist-release_60/lib/Headers/avx512vlvbmi2intrin.h ============================================================================== --- vendor/clang/dist-release_60/lib/Headers/avx512vlvbmi2intrin.h Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Headers/avx512vlvbmi2intrin.h Wed Jun 27 19:14:32 2018 (r335722) @@ -31,13 +31,8 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512vl,avx512vbmi2"))) -static __inline __m128i __DEFAULT_FN_ATTRS -_mm128_setzero_hi(void) { - return (__m128i)(__v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 }; -} - static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_mask_compress_epi16(__m128i __S, __mmask8 __U, __m128i __D) +_mm_mask_compress_epi16(__m128i __S, __mmask8 __U, __m128i __D) { return (__m128i) __builtin_ia32_compresshi128_mask ((__v8hi) __D, (__v8hi) __S, @@ -45,15 +40,15 @@ _mm128_mask_compress_epi16(__m128i __S, __mmask8 __U, } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_maskz_compress_epi16(__mmask8 __U, __m128i __D) +_mm_maskz_compress_epi16(__mmask8 __U, __m128i __D) { return (__m128i) __builtin_ia32_compresshi128_mask ((__v8hi) __D, - (__v8hi) _mm128_setzero_hi(), + (__v8hi) _mm_setzero_si128(), __U); } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_mask_compress_epi8(__m128i __S, __mmask16 __U, __m128i __D) +_mm_mask_compress_epi8(__m128i __S, __mmask16 __U, __m128i __D) { return (__m128i) __builtin_ia32_compressqi128_mask ((__v16qi) __D, (__v16qi) __S, @@ -61,29 +56,29 @@ _mm128_mask_compress_epi8(__m128i __S, __mmask16 __U, } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_maskz_compress_epi8(__mmask16 __U, __m128i __D) +_mm_maskz_compress_epi8(__mmask16 __U, __m128i __D) { return (__m128i) __builtin_ia32_compressqi128_mask ((__v16qi) __D, - (__v16qi) _mm128_setzero_hi(), + (__v16qi) _mm_setzero_si128(), __U); } static __inline__ void __DEFAULT_FN_ATTRS -_mm128_mask_compressstoreu_epi16(void *__P, __mmask8 __U, __m128i __D) +_mm_mask_compressstoreu_epi16(void *__P, __mmask8 __U, __m128i __D) { __builtin_ia32_compressstorehi128_mask ((__v8hi *) __P, (__v8hi) __D, __U); } static __inline__ void __DEFAULT_FN_ATTRS -_mm128_mask_compressstoreu_epi8(void *__P, __mmask16 __U, __m128i __D) +_mm_mask_compressstoreu_epi8(void *__P, __mmask16 __U, __m128i __D) { __builtin_ia32_compressstoreqi128_mask ((__v16qi *) __P, (__v16qi) __D, __U); } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_mask_expand_epi16(__m128i __S, __mmask8 __U, __m128i __D) +_mm_mask_expand_epi16(__m128i __S, __mmask8 __U, __m128i __D) { return (__m128i) __builtin_ia32_expandhi128_mask ((__v8hi) __D, (__v8hi) __S, @@ -91,15 +86,15 @@ _mm128_mask_expand_epi16(__m128i __S, __mmask8 __U, __ } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_maskz_expand_epi16(__mmask8 __U, __m128i __D) +_mm_maskz_expand_epi16(__mmask8 __U, __m128i __D) { return (__m128i) __builtin_ia32_expandhi128_mask ((__v8hi) __D, - (__v8hi) _mm128_setzero_hi(), + (__v8hi) _mm_setzero_si128(), __U); } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_mask_expand_epi8(__m128i __S, __mmask16 __U, __m128i __D) +_mm_mask_expand_epi8(__m128i __S, __mmask16 __U, __m128i __D) { return (__m128i) __builtin_ia32_expandqi128_mask ((__v16qi) __D, (__v16qi) __S, @@ -107,15 +102,15 @@ _mm128_mask_expand_epi8(__m128i __S, __mmask16 __U, __ } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_maskz_expand_epi8(__mmask16 __U, __m128i __D) +_mm_maskz_expand_epi8(__mmask16 __U, __m128i __D) { return (__m128i) __builtin_ia32_expandqi128_mask ((__v16qi) __D, - (__v16qi) _mm128_setzero_hi(), + (__v16qi) _mm_setzero_si128(), __U); } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_mask_expandloadu_epi16(__m128i __S, __mmask8 __U, void const *__P) +_mm_mask_expandloadu_epi16(__m128i __S, __mmask8 __U, void const *__P) { return (__m128i) __builtin_ia32_expandloadhi128_mask ((const __v8hi *)__P, (__v8hi) __S, @@ -123,15 +118,15 @@ _mm128_mask_expandloadu_epi16(__m128i __S, __mmask8 __ } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_maskz_expandloadu_epi16(__mmask8 __U, void const *__P) +_mm_maskz_expandloadu_epi16(__mmask8 __U, void const *__P) { return (__m128i) __builtin_ia32_expandloadhi128_mask ((const __v8hi *)__P, - (__v8hi) _mm128_setzero_hi(), + (__v8hi) _mm_setzero_si128(), __U); } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_mask_expandloadu_epi8(__m128i __S, __mmask16 __U, void const *__P) +_mm_mask_expandloadu_epi8(__m128i __S, __mmask16 __U, void const *__P) { return (__m128i) __builtin_ia32_expandloadqi128_mask ((const __v16qi *)__P, (__v16qi) __S, @@ -139,19 +134,13 @@ _mm128_mask_expandloadu_epi8(__m128i __S, __mmask16 __ } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_maskz_expandloadu_epi8(__mmask16 __U, void const *__P) +_mm_maskz_expandloadu_epi8(__mmask16 __U, void const *__P) { return (__m128i) __builtin_ia32_expandloadqi128_mask ((const __v16qi *)__P, - (__v16qi) _mm128_setzero_hi(), + (__v16qi) _mm_setzero_si128(), __U); } -static __inline __m256i __DEFAULT_FN_ATTRS -_mm256_setzero_hi(void) { - return (__m256i)(__v16hi){ 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 }; -} - static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_mask_compress_epi16(__m256i __S, __mmask16 __U, __m256i __D) { @@ -164,7 +153,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_maskz_compress_epi16(__mmask16 __U, __m256i __D) { return (__m256i) __builtin_ia32_compresshi256_mask ((__v16hi) __D, - (__v16hi) _mm256_setzero_hi(), + (__v16hi) _mm256_setzero_si256(), __U); } @@ -180,7 +169,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_maskz_compress_epi8(__mmask32 __U, __m256i __D) { return (__m256i) __builtin_ia32_compressqi256_mask ((__v32qi) __D, - (__v32qi) _mm256_setzero_hi(), + (__v32qi) _mm256_setzero_si256(), __U); } @@ -210,7 +199,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_maskz_expand_epi16(__mmask16 __U, __m256i __D) { return (__m256i) __builtin_ia32_expandhi256_mask ((__v16hi) __D, - (__v16hi) _mm256_setzero_hi(), + (__v16hi) _mm256_setzero_si256(), __U); } @@ -226,7 +215,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_maskz_expand_epi8(__mmask32 __U, __m256i __D) { return (__m256i) __builtin_ia32_expandqi256_mask ((__v32qi) __D, - (__v32qi) _mm256_setzero_hi(), + (__v32qi) _mm256_setzero_si256(), __U); } @@ -242,7 +231,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_maskz_expandloadu_epi16(__mmask16 __U, void const *__P) { return (__m256i) __builtin_ia32_expandloadhi256_mask ((const __v16hi *)__P, - (__v16hi) _mm256_setzero_hi(), + (__v16hi) _mm256_setzero_si256(), __U); } @@ -258,7 +247,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_maskz_expandloadu_epi8(__mmask32 __U, void const *__P) { return (__m256i) __builtin_ia32_expandloadqi256_mask ((const __v32qi *)__P, - (__v32qi) _mm256_setzero_hi(), + (__v32qi) _mm256_setzero_si256(), __U); } @@ -270,23 +259,23 @@ _mm256_maskz_expandloadu_epi8(__mmask32 __U, void cons (__mmask8)(U)); }) #define _mm256_maskz_shldi_epi64(U, A, B, I) \ - _mm256_mask_shldi_epi64(_mm256_setzero_hi(), (U), (A), (B), (I)) + _mm256_mask_shldi_epi64(_mm256_setzero_si256(), (U), (A), (B), (I)) #define _mm256_shldi_epi64(A, B, I) \ _mm256_mask_shldi_epi64(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I)) -#define _mm128_mask_shldi_epi64(S, U, A, B, I) __extension__ ({ \ +#define _mm_mask_shldi_epi64(S, U, A, B, I) __extension__ ({ \ (__m128i)__builtin_ia32_vpshldq128_mask((__v2di)(A), \ (__v2di)(B), \ (int)(I), \ (__v2di)(S), \ (__mmask8)(U)); }) -#define _mm128_maskz_shldi_epi64(U, A, B, I) \ - _mm128_mask_shldi_epi64(_mm128_setzero_hi(), (U), (A), (B), (I)) +#define _mm_maskz_shldi_epi64(U, A, B, I) \ + _mm_mask_shldi_epi64(_mm_setzero_si128(), (U), (A), (B), (I)) -#define _mm128_shldi_epi64(A, B, I) \ - _mm128_mask_shldi_epi64(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I)) +#define _mm_shldi_epi64(A, B, I) \ + _mm_mask_shldi_epi64(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I)) #define _mm256_mask_shldi_epi32(S, U, A, B, I) __extension__ ({ \ (__m256i)__builtin_ia32_vpshldd256_mask((__v8si)(A), \ @@ -296,23 +285,23 @@ _mm256_maskz_expandloadu_epi8(__mmask32 __U, void cons (__mmask8)(U)); }) #define _mm256_maskz_shldi_epi32(U, A, B, I) \ - _mm256_mask_shldi_epi32(_mm256_setzero_hi(), (U), (A), (B), (I)) + _mm256_mask_shldi_epi32(_mm256_setzero_si256(), (U), (A), (B), (I)) #define _mm256_shldi_epi32(A, B, I) \ _mm256_mask_shldi_epi32(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I)) -#define _mm128_mask_shldi_epi32(S, U, A, B, I) __extension__ ({ \ +#define _mm_mask_shldi_epi32(S, U, A, B, I) __extension__ ({ \ (__m128i)__builtin_ia32_vpshldd128_mask((__v4si)(A), \ (__v4si)(B), \ (int)(I), \ (__v4si)(S), \ (__mmask8)(U)); }) -#define _mm128_maskz_shldi_epi32(U, A, B, I) \ - _mm128_mask_shldi_epi32(_mm128_setzero_hi(), (U), (A), (B), (I)) +#define _mm_maskz_shldi_epi32(U, A, B, I) \ + _mm_mask_shldi_epi32(_mm_setzero_si128(), (U), (A), (B), (I)) -#define _mm128_shldi_epi32(A, B, I) \ - _mm128_mask_shldi_epi32(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I)) +#define _mm_shldi_epi32(A, B, I) \ + _mm_mask_shldi_epi32(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I)) #define _mm256_mask_shldi_epi16(S, U, A, B, I) __extension__ ({ \ (__m256i)__builtin_ia32_vpshldw256_mask((__v16hi)(A), \ @@ -322,23 +311,23 @@ _mm256_maskz_expandloadu_epi8(__mmask32 __U, void cons (__mmask16)(U)); }) #define _mm256_maskz_shldi_epi16(U, A, B, I) \ - _mm256_mask_shldi_epi16(_mm256_setzero_hi(), (U), (A), (B), (I)) + _mm256_mask_shldi_epi16(_mm256_setzero_si256(), (U), (A), (B), (I)) #define _mm256_shldi_epi16(A, B, I) \ _mm256_mask_shldi_epi16(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I)) -#define _mm128_mask_shldi_epi16(S, U, A, B, I) __extension__ ({ \ +#define _mm_mask_shldi_epi16(S, U, A, B, I) __extension__ ({ \ (__m128i)__builtin_ia32_vpshldw128_mask((__v8hi)(A), \ (__v8hi)(B), \ (int)(I), \ (__v8hi)(S), \ (__mmask8)(U)); }) -#define _mm128_maskz_shldi_epi16(U, A, B, I) \ - _mm128_mask_shldi_epi16(_mm128_setzero_hi(), (U), (A), (B), (I)) +#define _mm_maskz_shldi_epi16(U, A, B, I) \ + _mm_mask_shldi_epi16(_mm_setzero_si128(), (U), (A), (B), (I)) -#define _mm128_shldi_epi16(A, B, I) \ - _mm128_mask_shldi_epi16(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I)) +#define _mm_shldi_epi16(A, B, I) \ + _mm_mask_shldi_epi16(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I)) #define _mm256_mask_shrdi_epi64(S, U, A, B, I) __extension__ ({ \ (__m256i)__builtin_ia32_vpshrdq256_mask((__v4di)(A), \ @@ -348,23 +337,23 @@ _mm256_maskz_expandloadu_epi8(__mmask32 __U, void cons (__mmask8)(U)); }) #define _mm256_maskz_shrdi_epi64(U, A, B, I) \ - _mm256_mask_shrdi_epi64(_mm256_setzero_hi(), (U), (A), (B), (I)) + _mm256_mask_shrdi_epi64(_mm256_setzero_si256(), (U), (A), (B), (I)) #define _mm256_shrdi_epi64(A, B, I) \ _mm256_mask_shrdi_epi64(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I)) -#define _mm128_mask_shrdi_epi64(S, U, A, B, I) __extension__ ({ \ +#define _mm_mask_shrdi_epi64(S, U, A, B, I) __extension__ ({ \ (__m128i)__builtin_ia32_vpshrdq128_mask((__v2di)(A), \ (__v2di)(B), \ (int)(I), \ (__v2di)(S), \ (__mmask8)(U)); }) -#define _mm128_maskz_shrdi_epi64(U, A, B, I) \ - _mm128_mask_shrdi_epi64(_mm128_setzero_hi(), (U), (A), (B), (I)) +#define _mm_maskz_shrdi_epi64(U, A, B, I) \ + _mm_mask_shrdi_epi64(_mm_setzero_si128(), (U), (A), (B), (I)) -#define _mm128_shrdi_epi64(A, B, I) \ - _mm128_mask_shrdi_epi64(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I)) +#define _mm_shrdi_epi64(A, B, I) \ + _mm_mask_shrdi_epi64(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I)) #define _mm256_mask_shrdi_epi32(S, U, A, B, I) __extension__ ({ \ (__m256i)__builtin_ia32_vpshrdd256_mask((__v8si)(A), \ @@ -374,23 +363,23 @@ _mm256_maskz_expandloadu_epi8(__mmask32 __U, void cons (__mmask8)(U)); }) #define _mm256_maskz_shrdi_epi32(U, A, B, I) \ - _mm256_mask_shrdi_epi32(_mm256_setzero_hi(), (U), (A), (B), (I)) + _mm256_mask_shrdi_epi32(_mm256_setzero_si256(), (U), (A), (B), (I)) #define _mm256_shrdi_epi32(A, B, I) \ _mm256_mask_shrdi_epi32(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I)) -#define _mm128_mask_shrdi_epi32(S, U, A, B, I) __extension__ ({ \ +#define _mm_mask_shrdi_epi32(S, U, A, B, I) __extension__ ({ \ (__m128i)__builtin_ia32_vpshrdd128_mask((__v4si)(A), \ (__v4si)(B), \ (int)(I), \ (__v4si)(S), \ (__mmask8)(U)); }) -#define _mm128_maskz_shrdi_epi32(U, A, B, I) \ - _mm128_mask_shrdi_epi32(_mm128_setzero_hi(), (U), (A), (B), (I)) +#define _mm_maskz_shrdi_epi32(U, A, B, I) \ *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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